Tomoaki Hatayama

Improved Inversion Channel Mobility in 4H-SiC MOSFETs on Si Face Utilizing Phosphorus-Doped Gate Oxide

We propose a new technique for fabricating 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with high inversion channel mobility. P atoms were incorporated into the SiO₂/4H-SiC (0001) interface by postoxidation annealing using phosphoryl chloride (POCl₃). The interface state density near the conduction band edge of 4H-SiC was reduced significantly, and the peak field-effect mobility of lateral 4H-SiC MOSFETs on (0001) Si face was improved to 89 cm²/V · s by POCl₃ annealing at 1000°C.

Field-test analysis of PV system output characteristics focusing on module temperature

Abstract Field-test data from a 50 kW photovoltaic (PV) system installed at The Nara Institute of Science and Technology (NAIST) were analyzed in detail. We found that the PV system operated in a wide temperature range and was strongly affected by the temperature coefficient of conversion efficiency when the module temperature became high. The temperature coefficient dependence of the system performance was analyzed in order to estimate the annual output of the system in an actual operating environment. As a result, it was found that the annual output energy of the PV system increased about 1% by an improvement of 0.1%/°C in the temperature coefficient. This result indicates that it is very important to consider the temperature characteristics in solar cell development.

Floating Nanodot Gate Memory Devices Based on Biomineralized Inorganic Nanodot Array as a Storage Node

The memory effect in floating nanodot gate field-effect-transistor (FET) was investigated by fabricating biomineralized inorganic nanodot embedded metal–oxide–semiconductor (MOS) devices. Artificially biomineralized cobalt (Co) oxide cores accommodated in ferritins were utilized as a charge storage node of floating gate memory. Two dimensional array of Co oxide core accommodated ferritin were, after selective protein elimination, buried into the stacked dielectric layers of MOS capacitors and MOSFETs. Fabricated MOS capacitors and MOSFETs presented a clear hysteresis in capacitance–voltage (C–V) characteristics and drain current–gate voltage (ID–VG) characteristics, respectively. The observed hysteresis in C–V and ID–VG are attributed to the electron and hole confinement within the embedded ferritin cores. These results clearly support the biologically synthesized cores work as charge storage nodes. This work proved the feasibility of the biological path for fabrication of electronic device components.

Removal of near-interface traps at SiO2/4H–SiC (0001) interfaces by phosphorus incorporation

Effective removal of near-interface traps (NITs) in SiO2/4H–SiC (0001) structures through phosphorus incorporation is demonstrated in this paper. Low-temperature capacitance-voltage and thermal dielectric relaxation current measurements were employed to investigate NITs in oxides prepared by dry oxidation, NO annealing, and POCl3 annealing. Both the measurements revealed that the density of electrons trapped in NITs in POCl3-annealed oxide is smaller than that in dry and NO-annealed oxides. The drastic elimination of NITs lowers the interface state density and increases the channel mobility in 4H–SiC metal-oxide-semiconductor field-effect transistors.

Thermal Analysis of Degradation in Ga2O3-In2O3-ZnO Thin-Film Transistors

Degradation of Ga2O3–In2O3–ZnO (GIZO) thin-film transistors (TFTs), which are promising for driving circuits of next-generation displays, was studied. We found a degradation mode that was not observed in silicon TFTs. A parallel shift without any change of the transfer curve was observed under gate voltage stress. Judging from the bias voltage dependences we confirmed that the mode was mainly dominated by a vertical electric field. Thermal distribution was measured to analysis the degradation mechanism. Joule heating caused by drain current was observed; however, a marked acceleration of degradation by drain bias was not found. Therefore, we concluded that Joule heating did not accelerate degradation. Recovery of electrical properties independent of stress voltage were observed.

Hot Carrier Effects in Low-Temperature Polysilicon Thin-Film Transistors

We have studied the reliability of a low-temperature polysilicon (poly-Si) thin-film transistor (TFT). The drain avalanche hot electron effect was characterized by changing the stress gate and drain voltage dependence. Generation of hot carriers was confirmed using an emission microscope. It was found that the degradation was improved by the lightly doped drain (LDD) structure. A degradation model was proposed and analyzed along with a two-dimensional device simulator. Reasonable agreement with the experimental results was successfully obtained. It was found that the density of state (DOS) of poly-Si was increased by the hot carrier effect locally around the drain region.

Anomalously anisotropic channel mobility on trench sidewalls in 4H-SiC trench-gate metal-oxide-semiconductor field-effect transistors fabricated on 8° off substrates

Metal-oxide-semiconductor (MOS) channel properties in 4H-SiC trench-gate MOS field-effect transistors fabricated on 8° off substrates were characterized. The MOS channel was formed only on one side of the trench sidewalls. The MOS field effect transistor performance depended strongly on the MOS channel planes of (112¯0), (1¯1¯20), (11¯00), and (1¯100). The highest channel mobility of 43cm2∕Vs was obtained on (112¯0). However, only a half value of 21cm2∕Vs was observed on (1¯1¯20), which is the opposite face to (112¯0). The anomalously anisotropic channel mobility is discussed based on the deviation from the crystallographically accurate {112¯0} plane caused by the combination of substrate off angle and sloped trench sidewalls.

Gate Length Dependence of Hot Carrier Reliability in Low-Temperature Polycrystalline-Silicon P-Channel Thin Film Transistors

Degradation of p-channel thin film transistor (TFT) under dc stress was investigated. We found that ON current and field-effect mobility increased. In order to clarify the cause of the degradation, we measured the degradation for various gate and drain voltage stress conditions. We found that the drain avalanche hot carrier effect was dominant. Analysis using an emission microscope also suggested that hot carriers had a strong relation with the degradation. Gate length dependence was analyzed with a device simulator based on the model considering the electron traps in the oxide. Areas where hot electrons are generated are independent of the gate length, therefore, TFTs with smaller gate length undergo more damage. Comparison between the simulation and the experimental values suggested that this model is valid.

Photoluminescence on Li-Codoped ZnS:Tm Phosphor

Very strong sharp lines in luminescence of Tm3+ have been observed in Li-codoped ZnS:Tm phosphor. In particular, blue emission intensity was stronger as compared with that of infrared emission when the codoped Li concentration in ZnS:Tm was 0.1 at.%. As ZnS:Tm emits a broad band and very weak Tm3+ lines, the role of Li is proposed as follows: Li ions fill defects in the ZnS host, and hence excitation energy transfers from the ZnS host to Tm3+ very easily.

Threshold Voltage Instability in 4H-SiC MOSFETs With Phosphorus-Doped and Nitrided Gate Oxides

Threshold voltage instability was investigated for 4H-SiC MOSFETs with phosphorus-doped (POCl3-annealed) and nitrided (NO-annealed) gate oxides. Threshold voltage shift observed in the bidirectional drain current-gate voltage characteristics was evaluated using various gate voltage sweeps at room and elevated temperatures up to 200 °C. The threshold voltage shift was also studied after applying positive and negative bias-temperature stress. Two types of MOSFETs showed different instability characteristics, depending on gate biases and temperatures. These features were found to originate from the difference in trap density and trap location at/near the oxide/SiC interface and in the oxide. It is apparent that the oxide traps in phosphorus-doped oxides and near-interface traps in nitrided oxides are the main origin of the threshold voltage instability via capture and emission (in the case of oxide traps, only capture) of both electrons and holes.