Daibashish Gangopadhyay

Compressed Sensing System Considerations for ECG and EMG Wireless Biosensors

Compressed sensing (CS) is an emerging signal processing paradigm that enables sub-Nyquist processing of sparse signals such as electrocardiogram (ECG) and electromyogram (EMG) biosignals. Consequently, it can be applied to biosignal acquisition systems to reduce the data rate to realize ultra-low-power performance. CS is compared to conventional and adaptive sampling techniques and several system-level design considerations are presented for CS acquisition systems including sparsity and compression limits, thresholding techniques, encoder bit-precision requirements, and signal recovery algorithms. Simulation studies show that compression factors greater than 16X are achievable for ECG and EMG signals with signal-to-quantization noise ratios greater than 60 dB.

Compressive sampling of ECG bio-signals: Quantization noise and sparsity considerations

Compressed sensing (CS) is an emerging signal processing paradigm that enables the sub-Nyquist processing of sparse signals; i.e., signals with significant redundancy. Electrocardiogram (ECG) signals show significant time-domain sparsity that can be exploited using CS techniques to reduce energy consumption in an adaptive data acquisition scheme. A measurement matrix of random values is central to CS computation. Signal-to-quantization noise ratio (SQNR) results with ECG signals show that 5- and 6-bit Gaussian random coefficients are sufficient for compression factors up to 6X and from 8X-16X, respectively, whereas 6-bit uniform random coefficients are needed for 2X-16X compression ratios.

A 0.8–2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass

A reconfigurable bandpass continuous-time ΣΔ RF ADC tunable over the 0.8-2 GHz frequency range is presented. System- and circuit-level innovations provide low power consumption and reduced circuit complexity. The proposed architecture operates in both the first- and second-Nyquist zones to enable a wide tuning range from a fixed sampling frequency of 3.2 GHz. A fully-integrated on-chip quadrature phase-locked loop (QPLL) allows quadrature phase synchronization between a raised-cosine DAC and a quantizer. Implemented in 0.13 μm CMOS the fully-integrated prototype achieves SNDR values of 50 dB, 46 dB, and 40 dB over a 1 MHz bandwidth at 796.5 MHz, 1.001 GHz and 1.924 GHz carrier frequencies, respectively, with a total power consumption of 41 mW. The measured phase noise of the QPLL is -113 dBc/Hz at an offset frequency of 1 MHz and the reference spur is - 74.5 dBc. The RMS period jitter is 1.38 ps at 3.2 GHz.

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Compressed sensing (CS) is a rapidly emerging signal processing technique that enables accurate capture and reconstruction of sparse signals from only a fraction of Nyquist-rate samples, significantly reducing the data-rate and system power consumption. This paper presents an in-depth comparative study on current state-of-the-art CS reconstruction algorithms. Reliability, accuracy, noise tolerance, computation time and are used as key metrics. Further, experiments on ECG signals are used to assess performance on real-world bio-signals.

ADC in 0.13

Sub-Nyquist analog pre-processing of sparse signals is achieved using the emerging compressed sensing (CS) signal processing paradigm. Electrocardiogram (ECG) signals have been shown previously to have significant time-domain sparsity. It is shown herein that electromyogram (EMG) signals exhibit both time- and frequency-domain sparsity. Hence, CS techniques are advantageous in either domain in reducing the energy consumption in an adaptive data acquisition front-end that is part of a body area network (BAN). A measurement matrix of random values is central to CS computation. Signal-to-quantization-noise ratio (SQNR) results with EMG signals show that 6-bit (including sign) Gaussian random coefficients are sufficient for compression factors up to 18X. It is also shown that 6-bit uniform random coefficients are preferred for some EMG bio-signals.

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Low-power low-loop-bandwidth (BW) integer-N frequency synthesizers with low phase noise have been reported previously. However, achieving similar power/phase-noise performance for a fractional-N synthesizer with a wide loop BW along with excellent spur performance has been challenging. A conventional fractional-N synthesizer is clocked by a crystal oscillator operating at a reference frequency (fref) less than a few tens of megahertz. An attractive alternative is to replace the low-frequency crystal oscillator with an integer-N phase-locked loop operating at an fref of a few hundreds of megahertz. The advantages and challenges of designing such a wide-loop-BW fractional-N synthesizer for low phase noise, spur, and power consumption are considered, and an extended-phase-range type-I ΣΔ fractional-N frequency synthesizer is implemented with an optimal fref of 290 MHz. Measurement results show that the synthesizer operating at 2.4 GHz with a wide loop BW of 1.8 MHz attains an in-band phase noise of -110 dBc/Hz and a worst case fractional spur of -69 dBc. The digital-intensive 0.18-μm CMOS design consumes 14.1 mW. No quantization noise cancellation or charge pump linearization techniques are used.

m CMOS

Compressed sensing (CS) is an emerging signal processing technique that enables sub-Nyquist sampling of sparse signals such as electrocardiogram (ECG), electromyogram (EMG), and electroencephalogram (EEG) bio-signals. Future CS signal processing systems will exploit significant time- and/or frequency-domain sparsity to achieve ultra-low-power bio-signal acquisition in the analog, digital, or mixed-signal domains. A measurement matrix of random values is key to one form of CS computation. It has been shown for ECG and EMG signals that signal-to-quantization noise ratios (SQNR) > 60 dB with compression factors up to 16X are achievable using uniform or Gaussian 6-bit random coefficients. In this paper, 1-bit random coefficients are shown also to give compression factors up to 16X with similar SQNR performance. This approach reduces hardware and saves energy concomitant with 1-bit versus 6-bit signal processing.

Compressed sensing reconstruction: Comparative study with applications to ECG bio-signals

This paper presents a low power, high gain, fully differential ultra-wide bandwidth operational amplifier with wide dynamic range. The design uses two-stage gain, high swing common-mode feedback, ‘doublet-free’ pole-zero cancelation and gm-boosting techniques to increase the unity gain frequency to about 1.5 times that of the widely used class-A common source output stage at similar power consumption. Design and implementation results for a 2.3 GHz, 1.4–2.3V supply, fully differential op amp with 2.3V differential output swing and 65 dB low frequency gain in 0.18µm digital CMOS technology are presented.

Compressive sampling of EMG bio-signals

A direct-RF sampled band-pass ΣΔ modulator enables reconfigurable RF A/D conversion. It features a programmable narrow-band Q-enhanced low-noise amplifier and a phase-locked loop implemented using a low-phase-noise injection-locked harmonic-filtering quadrature voltage-controlled oscillator. The quadrature outputs of the PLL provide phase synchronization between a raised-cosine DAC and the quantizer. The three-tap raised-cosine finite-impulse response filter is embedded in the RF DAC. A complete sampling receiver demonstrates progress towards Software-Defined Radio (SDR) applications. Implemented in 0.13 µm CMOS, it consumes 41 mW and achieves maximum SNDR values of 50 dB, 46 dB and 40 dB over a 1 MHz bandwidth with 796.5 MHz, 1.001 GHz and 1.924 GHz input carrier frequencies. The measured PLL phase noise is −113 dBc/Hz at an offset frequency of 1 MHz with a −74.5 dBc carrier-reference spur; the RMS period jitter is 1.38 ps at 3.2 GHz.

A 2.4-GHz Extended-Range Type-I

A fully-integrated LNA in 0.18/xm CMOS simultaneously achieves high gain, low noise figure (NF), good third-order input intercept linearity (IIP3), and low DC bias current consumption: 19 dB, 2.4 dB, −14.2 dBm and 1.3 mA, respectively, from a 1.2 V supply. The single-ended LNA uses a common-gate common-source (CG-CS) topology and operates at 5.4 GHz for WLAN applications. Using gm — boosting, current-reuse and transformer-feedback techniques, the LNA mitigates several design issues seen in the widely used common-source common-source current-reuse (CS-CS) LNAs and improves the IIP3 of CG-CS schemes by 6 dB, without increasing power and area consumption.