Subhanshu Gupta

A 0.8–2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass

A reconfigurable bandpass continuous-time ΣΔ RF ADC tunable over the 0.8-2 GHz frequency range is presented. System- and circuit-level innovations provide low power consumption and reduced circuit complexity. The proposed architecture operates in both the first- and second-Nyquist zones to enable a wide tuning range from a fixed sampling frequency of 3.2 GHz. A fully-integrated on-chip quadrature phase-locked loop (QPLL) allows quadrature phase synchronization between a raised-cosine DAC and a quantizer. Implemented in 0.13 μm CMOS the fully-integrated prototype achieves SNDR values of 50 dB, 46 dB, and 40 dB over a 1 MHz bandwidth at 796.5 MHz, 1.001 GHz and 1.924 GHz carrier frequencies, respectively, with a total power consumption of 41 mW. The measured phase noise of the QPLL is -113 dBc/Hz at an offset frequency of 1 MHz and the reference spur is - 74.5 dBc. The RMS period jitter is 1.38 ps at 3.2 GHz.

\Sigma \Delta

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch.

ADC in 0.13

A new sigma-delta architecture employs feed-forward topology with digital summing. The feed-forward architecture reduces the signal swings of the integrators and hence modulator distortion while digital summing eliminates the need for a summing op-amp and makes the design more robust to comparator offsets. Applying this architecture to a 2-2 cascade ADC, we can achieve a 12b resolution over a 10MHz signal bandwidth with a sampling rate of 160 MSamples/sec. The topology is especially attractive for low-power and low-voltage applications.

\mu

A transmit-receive (T/R) switch is designed to operate at 10 GHz in a triple-well CMOS process. The transmit switch includes multiple parallel resonant networks to improve loss and isolation characteristics and the receive switch includes an impedance matching network and DC bias circuitry to increase linearity. A simple simulation model is proposed for linearity analysis of the receive switch. Finally, a figure-of-merit for T/R switches is proposed and used to compare previous published results.

m CMOS

Architectural schemes for low-power calibration of oversampled analog-to-digital (A/D) systems are presented. Conventional full-rate least-mean squares (LMS) calibration has two well-known limitations: slow convergence and increased computational complexity/power dissipation for higher adaptive filter orders and sampling frequencies. Half-(ƒs/2) and quarter-rate (ƒs/4) LMS calibration for oversampled A/D decimators are used to reduce the computational complexity. Noble identities and polyphase decimation are used to implement these schemes to match digital noise-cancellation filters (NCF) to the corresponding transfer functions of an analog fourth-order cascade sigma-delta (ΣΔ ADC. Energy savings up to 30% compared to conventional full-rate (ƒs) schemes are confirmed using an Altera Stratix II field-programmable gate array (FPGA). The analog front-end comprises a switched-capacitor 2–2 cascade ΣΔ ADC implemented in 0.13µm CMOS. Using differential-pair opamps with gains of only 22 db and an oversampling ratio OSR = 8, the ΣΔ ADC system achieves 11-bit accuracy over a 9.4 MHz bandwidth with SNR = 67 dB and SFDR = 75 dB.

Cascaded Complex ADCs With Adaptive Digital Calibration for

Emerging wireless standards aggregate information by selecting combinations of contiguous or non-contiguous channels, thereby enabling wider transmission bandwidths, and hence, higher data rates. Frequency-interleaved analog-to-digital conversion (FI-ADC) is an attractive emerging technique for carrier aggregation receivers because it facilitates an efficient way to dynamically vary the receiver bandwidth in order to address the many possible channel combinations. Compared to their time-interleaved counterparts, the specifications of the samplers in the parallel channels in FI-ADCs are significantly relaxed, thereby resulting in lower overall power consumption in the receiver. This work extends the FI-ADC concept to the quadrature frequency-interleaved oversampled data converter (QFI-ADC) to achieve greater aggregate data rates. Previously, digital-to-analog converter (DAC) and other inter-channel mismatches have limited the performance of QFI-ADCs. In this paper, we propose a low-complexity element rotation algorithm (ERA) to mitigate DAC mismatches. The ERA is synthesized from the corresponding mismatch transfer function using a rigorous mathematical procedure which is shown to be applicable generally to low-pass, high-pass, band-pass and quadrature ERAs. Simulations confirm that the resulting low-complexity quadrature ERAs have advantages over previously proposed approaches in both performance and hardware complexity. An additional gain calibration technique alleviates image folding due to gain and timing mismatches between the quadrature DAC elements, which yields higher SNDR.

I/Q

A scaling-friendly approach for the low-power calibration of oversampled analog-to-digital (A/D) systems is presented. A 22-dB amplifier relaxes the design constraints of the analog front-end (AFE). The integrator non-idealities in the AFE of the sigma-delta (ΣΔ) ADC are calibrated using a multi-rate polyphase least-mean squares (LMS) algorithm. The proposed half- (fs/2) and quarter-rate (fs/4) LMS calibration schemes reduce computational complexity and achieve more than 2.5× savings in digital power consumption for low-OSR (over-sampling ratio) ΔΣ ADCs, which require higher adaptive filter orders and sampling frequencies. The proposed scheme can have further applications in serial-link I/O and sub-band echo cancellation architectures.

Mismatch

A direct-RF sampled band-pass ΣΔ modulator enables reconfigurable RF A/D conversion. It features a programmable narrow-band Q-enhanced low-noise amplifier and a phase-locked loop implemented using a low-phase-noise injection-locked harmonic-filtering quadrature voltage-controlled oscillator. The quadrature outputs of the PLL provide phase synchronization between a raised-cosine DAC and the quantizer. The three-tap raised-cosine finite-impulse response filter is embedded in the RF DAC. A complete sampling receiver demonstrates progress towards Software-Defined Radio (SDR) applications. Implemented in 0.13 µm CMOS, it consumes 41 mW and achieves maximum SNDR values of 50 dB, 46 dB and 40 dB over a 1 MHz bandwidth with 796.5 MHz, 1.001 GHz and 1.924 GHz input carrier frequencies. The measured PLL phase noise is −113 dBc/Hz at an offset frequency of 1 MHz with a −74.5 dBc carrier-reference spur; the RMS period jitter is 1.38 ps at 3.2 GHz.

A Digital-Summing Feedforward Σ-Δ Modulator and its Application to a Cascade ADC

This work presents a near zero power relaxation oscillator for biomedical applications. Relaxation oscillators have now become a potential candidate for on-chip clock references due to their miniaturized sizes and integrating capability. In order to be suitable for biomedical applications, accurate and energyefficient oscillators are required. An ultra-low power relaxation oscillator with 20kHz oscillating frequency is implemented with 0.13μm CMOS process. A switched-current technique is proposed to reduce the power consumption without compromising the overall performance. The relaxation oscillator consumes 143nW power and has a temperature coefficient of 19.1ppm/°C with a phase noise of -93dBc/Hz at 1kHz offset frequency.

Design considerations for a 10 GHz CMOS transmit-receive switch

Approaches for modeling continuous-time (CT) SigmaDelta modulators based on the Bilinear (BT), Lossless-Discrete Integration (LDI) and Impulse Invariant (II) transformations are compared for low-OSR cascade architectures. A hybrid modeling approach is introduced that combines the BT and LDI transformations, and enables direct synthesis of the CT modulator from a discrete-time (DT) template. The resulting CT architecture is identical to the DT counterpart; i.e., no new signal paths are introduced. Moreover, frequency warping is not required as in the BT case for low-OSR modulators.