Daisuke Ryuzaki

Heat and Moisture Resistance of Siloxane-Based Low-Dielectric-Constant Materials

Resistance of siloxane-based, low-dielectric-constant (low-k) dielectrics against heat and moisture stress is clarified. The organo-silica-glass (OSG) and the silicon-oxycarbide are shown to be the most reliable: the k-values are stable even after a heating test at 650°C and a pressure cooker treatment for 100 h. This stability is high enough to ensure the low-k property throughout fabricating multilevel interconnects and long-term reliability alter the fabrication. This is shown to be due to the stability of Si-CH 3 bonds and Si-CH n -Si bonds incorporated in the OSG and the silicon-oxycarbide. The stability of the OSG in real low-k interlevel dielectric structure was also demonstrated using four-level interconnect test devices. The low-k property still remains even after the reliability tests, showing that the low-k interlayer dielectric structure is sufficiently resistant to heat and moisture stresses.

Characterization of Line-Edge Roughness in Cu/Low-k Interconnect Pattern

To establish a method of measuring interconnect line-edge roughness (LER), low-k line patterns were observed and electric field concentration was simulated on the basis of observation results. Wedge-shaped LERs were observed at the edges of low-k lines, and the bottom and the top widths of the average wedge feature were 60 and 7 nm (or smaller), respectively. Simulation showed that LER causes serious electric field concentration, which may cause the degradation of time-dependent dielectric breakdown (TDDB) lifetime at 100-nm-pitch Cu/low-k interconnects. The maximum electric field strength depends on the conventional LER metric 3Rq, but depends more strongly on the wedge angle, the curvature of the tip. That is, other metrics such as wedge angle can predict fatal electric field concentration caused by LER than the conventional metric 3Rq.

Characterization of line-edge roughness in Cu/low-k interconnect pattern

To establish a method for measuring interconnect line-edge roughness (LER), low-k line patterns were observed and electric-field concentration was simulated based on the observation results. Wedges were observed on the edges, and the bottom and the top widths of the average wedge feature were 60 nm and 7 nm (or smaller), respectively. Simulation showed that the LER causes serious degradation of TDDB immunity at 100-nm-pitch Cu/low-k interconnects. The maximum electric-field intensity depends upon the conventional LER metric, 3Rq, but depends more strongly on the wedge angle, the curvature of the tip, and the minimum linewidth.

Enhanced dielectric-constant reliability of low-k porous organosilicate glass (k = 2.3) for 45-nm-generation Cu interconnects

The mechanism of the dielectric-constant increase in porous organosilicate glasses (OSGs) under electric-field stress has been revealed for the first time, where the dielectric-constant increase is caused by the oxidation of methyl groups in porous OSGs. By optimizing the methyl content, the authors developed a highly reliable, novel low-k porous OSG (k =2.3) with a dielectric-constant lifetime of 10/sup 3/ years for 45-nm-generation copper interconnects. The newly developed porous OSG was successfully integrated into 240-nm-pitch copper interconnects, where the line-to-line capacitance shows a much longer lifetime than the case of conventional porous OSGs.

Time-Dependent Dielectric-Constant Increase Reliability Issue for Low Dielectric-Constant Materials

The stability of low dielectric-constant (low-k) materials during electric-field stress was studied. The dielectric constants (k-values) were found to increase sharply under bias-temperature stress. This time-dependent dielectric-constant increase (TDDI) was estimated for a practical operating condition by extrapolation. The extrapolated TDDI lifetimes and k-value increases for tested materials (k = 2.3-3.2) ranged from 30 days to 1,000 years and from 0 to 23%, respectively. Considering the estimated TDDI, new criteria for reliable low-k materials are proposed. The criteria were used successfully to identify those low-k materials that show high stability during electric-field stress.

Copper-induced dielectric breakdown in silicon oxide deposited by plasma-enhanced chemical vapor deposition using trimethoxysilane

The barrier mechanism against copper-ion diffusion in silicon-oxide films deposited by plasma-enhanced chemical vapor deposition (PECVD) using trimethoxysilane (TMS) and nitrous oxide (N2O) chemistry (PE-TMS oxide) was studied. It was found that the flow ratio of TMS gas to N2O gas during deposition strongly affects a time-dependent dielectric-breakdown lifetime of PE-TMS oxide with a copper electrode as well as other PE-TMS oxide film properties such as electrical properties (leakage current and dielectric constant), a physical property (atomic composition), and chemical properties (chemical bonding states and wet-etching rate). The dielectric-breakdown lifetime of PE-TMS oxide film with a copper anode is a maximum at a source-gas ratio ranging from 1.7% to 3.3%. On the other hand, leakage current density, wet-etch rate, and dielectric-breakdown lifetime of PE-TMS oxide film with an aluminum electrode are degraded by increasing the source-gas flow ratio (0.83% to 12%). These results suggest that two type...

Novel dissoluble hardmask for damage-less Cu/low-k interconnect fabrication

A Cu/low-k dual-damascene process using a novel dissoluble hardmask material, AlO, is developed to suppress ashing-damage to porous/nonporous low-k SiOC. In this process, ArF-resist patterns are firstly transferred to a very thin, typically 30-nm-thick, AlO hardmask layer. After removing the resist, SiOC is patterned using the hardmask. The hardmask remaining after the etching is spontaneously removed during post-etch wet-cleaning. The line-to-line capacitance of 280-nm-pitch, 4-level interconnects using this process is reduced by 10% from that using a conventional resist-mask process.

Dual-Damascene Cu/Low-k Interconnect Fabrication Scheme Using Dissoluble Hard Mask Material

A Cu-low-k dual-damascene scheme is developed by employing a dissoluble hard mask material, AlO. High-selectivity etching, over 15, is achieved by using the AlO hard mask. After the etching, the remaining AlO dissolves ina postetch cleaning solution, making additional processing costs minimal. By using this scheme, the line-to-line capacitance reduces by 10% because no ashing is applied after low-k trench etching. Low-temperature deposition of AlO is found to be the key for the dissoluble property. When the deposition temperature is 100°C or less. a wide range of conventional postetch cleaning solutions can be used to remove the remaining AlO hard mask.

Direct Resist Removal Process from Copper-Exposed Vias for Low-Parasitic-Capacitance Interconnects

A resist stripping process from Cu-exposed vias is developed to reduce the thickness of high permittivity (high-k) SiN in Cu/low-k interconnects. A low power, low temperature O 2 reactive ion etch is proposed to suppress the significant Cu oxidation. Additionally, removing Si contents from the Cu surface is found to be critical, This resist stripping process is successfully applied to the fabrication of Cu/low-k interconnect test devices using silicon oxycarbide (k = 3.3). Low resistance, 0.25 μm diam via connections were achieved. Time dependent dielectric breakdown lifetime tests showed that even 25 nm thick SiN has a sufficient barrier property against Cu diffusion, showing that the SiN thickness reduction is also feasible from the reliability viewpoint. By thinning SiN to less than 25 nm, over 5-10% reduction in k can be achieved even when using the same low-k interlevel dielectric.

Simple, reliable Cu/low-k interconnect integration using mechanically-strong low-k dielectric material: silicon-oxycarbide

A new low-k material (silicon-oxycarbide, k=3.3) is developed to improve the mechanical strength of Cu/low-k interconnects. The film is shown to be over three-times stronger than conventional ones. The film qualities are high enough: the heat resistance is goad up to 650/spl deg/C, and the breakdown voltage is 55 MV/cm. The film is applied to interconnection test devices without using an oxide-cap. The k remains as low as 3.3, showing that an equivalent capacitance reduction with conventional materials (k=2.5-2.9) can be achieved using a simpler and more reliable structure.