Takeshi Furusawa

UV-hardened high-modulus CVD-ULK material for 45-nm node Cu/low-k interconnects with homogeneous dielectric structures

A UV-hardened high-modulus ULK (ultra low-k) material is proposed for 45-nm-node Cu/low-k interconnects with homogeneous dielectric structures. An elastic modulus as high as 16 GPa was achieved for the ULK material with k=2.65. By combining this material with an advanced dielectric barrier (k=3.7), interconnect test devices with 65-nm-node dimensions were fabricated. The UV-hardened high-modulus ULK material is shown to be effective in improving electrical performance while maintaining sufficient mechanical integrity.

Constant field stressing of via-to-line spacing for accurate projection of intrinsic TDDB lifetime

We proposed solutions for determining the accurate projection of the TDDB lifetime of via-to-line spacing; that is, using a single-via test structure and constant field stress. This method eliminates the lifetime variations due to the spacing variations more effectively than conventional methods, for example, area scaling. The projected lifetime under the given use conditions increased at least about two-orders of magnitude by using this method, showing that constant field stress can be used to effectively project intrinsic TDDB lifetimes.

Capturing intrinsic impact of low-k dielectric stacks and packaging materials on mechanical integrity of Cu/low-k interconnects

We present a methodology for capturing the intrinsic impact of both low-k dielectric stacks and packaging materials on the mechanical integrity of Cu/low-k interconnects. This drastically reduces the time and cost of sample fabrication and reliability tests and provides short-cycle feedback for both low-k and packaging materials development. Furthermore, this methodology is applicable for all types of packaging, from low-cost QFPs to high-performance Pb-free FCBGAs.

Comprehensive lifetime prediction for intrinsic and extrinsic TDDB failures in Cu/Low-k interconnects

We present a comprehensive lifetime prediction methodology for both intrinsic and extrinsic Time-Dependent Dielectric Breakdown (TDDB) failures to provide adequate Design-for-Reliability. For intrinsic failures, we propose applying the √E model and estimating the Weibull slope using dedicated single-via test structures. This effectively prevents lifetime underestimation, and thus relaxes design restrictions. For extrinsic failures, we propose applying the thinning model and Critical Area Analysis (CAA). In the thinning model, random defects reduce effective spaces between interconnects, causing TDDB failures. We can quantify the failure probabilities by using CAA for any design layouts of various LSI products.

Stress Engineering in CuILow-k Interconnects by using UV-Cure of Cu Diffusion Barrier Dielectrics

In this paper, we discuss the possibility of stress engineering in the Cu/low-k interconnect reliability. We mention the film characteristics of UV cured SiCN and SiCO. A large stress change from compressive to tensile stress was observed. Through TEG demonstration, it was found that UV-cured SiCN and SiCO film make it possible to reduce SIV failure without degradation to other interconnect reliability