Richard Burch

A Monte Carlo approach for power estimation

The authors investigate a power estimation technique for VLSI that combines the accuracy of simulation-based techniques with the speed of the probabilistic techniques. The resulting method is statistical in nature; it consists of applying randomly generated input patterns to the circuit and monitoring, with a simulator, the resulting power value. This is continued until a value of power is obtained with a desired accuracy, at a specified confidence level. The authors present the algorithm and experimental results, and discuss the superiority of the approach. >

Probabilistic simulation for reliability analysis of CMOS VLSI circuits

A current-estimation approach to support the analysis of electromigration (EM) failures in power supply and ground buses of CMOS VLSI circuits is discussed. It uses the original concept of probabilistic simulation to efficiently generate accurate estimates of the expected current waveform required for electromigration analysis. Thus, the approach is pattern-independent and relieves the designer of the tedious task of specifying logical input waveforms. This approach has been implemented in the program CREST (current estimator) which has shown excellent accuracy and dramatic speedups compared with traditional approaches. The approach and its implementation are described, and the results of numerous CREST runs on real circuits are presented. >

McPOWER: a Monte Carlo approach to power estimation

An alternative technique for power estimation that combines the accuracy of simulation-based techniques with the speed of the probabilistic technique is investigated. The resulting method is statistical in nature; it consists of applying randomly-generated input patterns to the circuit and monitoring, with a simulator, the resulting power value. This is continued until a value of power is obtained with a desired accuracy, at a specified confidence level. The algorithm and experimental results are presented and the superiority of this approach is discussed.<<ETX>>

Pattern-independent current estimation for reliability analysis of CMOS circuits

Accurate and efficient expected current is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, etc. A pattern-independent simulation approach for estimating this expected current waveform drawn by CMOS circuitry has been developed. Four original concepts are presented which allow an efficient and accurate estimation of expected current waveforms. They are: probability waveforms, probability waveform propagation, probabilistic circuit models, and statistical timing analysis. This approach is considerably faster than traditional methods and yields comparable results.<<ETX>>

CREST-a current estimator for CMOS circuits

CREST is a pattern-independent current estimation approach developed to support electromigration analysis tools. It uses the powerful, original concept of probabilistic simulation to generate accurate estimates of the expected current waveforms efficiently. The original implementation of CREST is extended to circuits containing pass transistors, reconvergent fanout, and feedback, and heuristics to simulate circuits with large reconvergent fanout or feedback blocks efficiently are provided. The results of using CREST on several real circuits are presented.<<ETX>>

Direct circuit simulation algorithms for parallel processing (VLSI)

The improvement in computational throughput of VLSI circuit simulation is addressed. A high degree of natural parallelism exists in the circuit simulation problem; potentially a large number of processor can be used efficiently. Three distinct approaches for obtaining parallel execution in direct-method circuit simulators are investigated. These approaches differ primarily in the size of the individual tasks used to obtain parallel execution. The relative advantages of each approach are examined, and performance data from simulations on parallel processing systems are presented. For the third approach, very good parallel efficiency was obtained; in some cases, 99% parallelism has been observed. >

A methodology for the top-down synthesis of semiconductor process flows

Increasing expense of developing microelectronic manufacturing technology threatens to slow the growth of the electronics industry. This paper describes the progress we have made in developing methodologies and techniques to reduce the cost of designing microelectronic manufacturing flows. Our approach is to partition the task of process flow design into a number of abstraction levels and provide mechanisms to translate between these levels. This approach results in a top-down design methodology where requirements from higher levels of abstraction are successively reduced to lower abstraction levels, while meeting the constraints imposed by the lower levels. The paper enumerates the abstraction levels we have identified so far, and describes the translation mechanisms for a class of process design tasks: modification of an existing flow in response to change in performance requirements. Finally, we briefly describe a design environment that incorporates these ideas.

New implicit integration method for efficient latency exploitation in circuit simulation

To exploit time-domain latency in circuit simulation using direct methods, an accurate, computationally efficient model for slowly moving, dormant portions of the circuit is required. A new, implicit integration method, the overdetermined polynomial method (ODPM), has been developed which permits the formulation of an accurate latent model. Using the ODPM integration method, the Jacobian of a dormant subcircuit need not be reevaluated over a large number of time steps of varying size. An accurate Norton equivalent circuit that emulates the impedance and current characteristics of the subcircuit can be obtained without reevaluation of the Jacobian or nonlinear charge computations. This new approach for utilizing latency produces significant improvements in circuit simulation speed with no decrease in accuracy or generality. The authors have demonstrated speed gains of 3 to 20 times over TISPICE for several large circuits. >

Automatic synthesis of equipment recipes from specified wafer-state transitions

Run-to-run and supervisory control algorithms determine the equipment recipe to produce a desired output wafer state given the incoming wafer state and the current equipment model. For simple, low-dimensional equipment models, this problem is not difficult. However, when there are multiple responses for the system and the equipment models are nonlinear, automated synthesis of recipes is complicated by the potential for multiple solutions. While there are standard techniques for handling such inverse problems in general, each of these techniques is optimal only under certain conditions. We present a framework for performing automated synthesis of recipes that integrates database search, local optimization, and global optimization into a consistent methodology that is applicable to a wide range of equipment models and inversion problems in general. The integrated framework imposes quasi-continuity on the extracted recipes, is scalable to systems of high dimensionality, and can be optimized to minimize the expected synthesis time for any given problem. The framework has been implemented in a system that performs statistical optimization of CMOS transistor designs. The integrated framework provides a factor of 16 increase in performance over global optimization and a factor of three increase over exhaustive search and multiple starts of a local optimizer.

A parallel block-diagonal preconditioned conjugate-gradient solution algorithm for circuit and device simulations

The authors present a general purpose, parallel matrix solver based on the conjugate gradient squared (CGS) method which features a novel preconditioning scheme commensurate with massive parallel computing. The solver algorithm has been successfully used for solving linear systems of equations arising from circuit and device simulations with MOS and bipolar junction transistor (BJT) circuits, both digital and analog, as well as high-level injection conditions in devices. The performance of the algorithm can be further improved by a matrix partitioning scheme.<<ETX>>