Dale L. Critchlow

Design and characteristics of n-channel insulated-gate field-effect transistors

An n-channel insulated-gate field-effect transistor technology established at IBM Research has served as the basis for further development leading to FET memory. Designs and characteristics of experimental devices of 500 and 1000 A gate insulator thicknesses are presented, with particular attention to the effects of source-drain spacing.

IGFET circuit performance-n-channel versus p-channel

The n-channel insulated-gate field-effect transistor offers a factor of 2 to 3.4 mobility advantage (depending on crystal orientation and substrate doping level) over p-channel devices. In addition, several advantages result from the fact that the work function difference between an aluminum gate and the silicon substrate is about -0.8 volt for a p substrate compared with about zero for an n substrate. In particular, this results in a low threshold voltage that allows the use of a substrate bias to adjust the threshold voltage over a useful design range resulting in an added flexibility in choice of thresholds and substrate doping, a reduction in the effect of source-substrate bias on device threshold, decreased junction capacitance, and larger parasitic thick-oxide thresholds for a given insulator thickness. The speed, power, and density advantages of the n-channel device are illustrated for logic and memory circuits using representative n- and p-channel device designs.

Esaki (tunnel)-diode logic circuits

The Esaki diode is a potentially low-cost, high-speed, two-terminal device exhibiting a short-circuit stable, negative resistance over a portion of its volt - ampere characteristic. Under suitable bias and loading conditions, Esaki-diode circuits can perform threshold logic and binary memory functions and can provide power gain when switched. The authors show several appropriately-biased diodes resistively coupled together such that bistable operation is obtained. The three-phase pulse-clock system shown maintains unilateral flow of information and also serves as an unconditional reset of the corresponding logic blocks. Transfer of information occurs during the period of overlap of adjacent clock pulses where the overlap is longer than the propagation time of the information. The propagation time is a function of the reactances associated with the circuit. The inclusion of reactive components in the coupling networks to provide temporary storage of information during switching eliminates the need for overlapping clock pulses. The capabilities of the various types of coupling will be discussed, and some quantitative results will be given in the presentation.

Esaki Diode Logic Circuits

The Esaki diode is a potentially low-cost, high-speed two-terminal device exhibiting a short-circuit-stable negative resistance over a portion of its volt-ampere characteristic. By proper biasing and loading, it can be used to perform power amplification and memory functions. In this paper, a variety of digital computer circuits (a result of an early exploratory program) is described which utilizes the above properties. In particular, shift registers, triggers, and counters are presented. The following shift registers are described: 1) A register which consists of one Esaki diode and one conventional diode per stage. Shifting is accomplished with a two-phase square-wave drive. The Esaki diode provides memory and power gain, and the conventional diode provides a unilateral flow of information. 2) A register which combines Esaki diodes with square-loop ferromagnetic cores. Again the Esaki diode provides memory and power gain. Upon application of a single-phase drive, the cores perform a gating operation depending upon the state of the diodes. 3) With the use of Esaki diode-transistor combinations, high-speed circuits are obtained which depend upon the Esaki diodes primarily for memory and the transistors for power gain and unilateral flow of information. The flip-flop and counter circuits to be presented are the following: 1) A binary counter using Esaki diodes with magnetic cores; 2) high-speed flipflops using Esaki diode-transistor combinations.

High Speed MOSFET Circuits Using Advanced Lithography

During the last decade we have seen a dramatic increase in the complexity of silicon integrated circuit chips, particularly in memory. The n-channel FET technology is dominant in main memory and in lower performance logic and arrays (i.e., read-only memory and buffers) because of its higher circuit density and simpler processing, whereas bipolar transistor technology dominates for high-performance logic and arrays.

Recollections on MOSFET Scaling

In mid-1970, Bob Dennard , Fritz Gaensslen and Larry Kuhn formalized the constant-field scaling theory and its limitations. Bob Dennard went on to contribute profoundly to the demonstration of the feasibility of MOSFET scaling and led the way into implementation in real products. Scaled CMOS has become the dominant technology for digital and many analog applications and will continue to be a fundamental driving force of the industry for years to come.