John K. DeBrosse

Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

Significant challenges face DRAM scaling toward and beyond the 0.10-µm generation. Scaling techniques used in earlier generations for the array-access transistor and the storage capacitor are encountering limitations which necessitate major innovation in electrical operating mode, structure, and processing. Although a variety of options exist for advancing the technology, such as low-voltage operation, vertical MOSFETs, and novel capacitor structures, uncertainties exist about which way to proceed. This paper discusses the interrelationships among the DRAM scaling requirements and their possible solutions. The emphasis is on trench-capacitor DRAM technology.

Design considerations for MRAM

MRAM (magnetic random access memory) technology, based on the use of magnetic tunnel junctions (MTJs) as memory elements, is a potentially fast nonvolatile memory technology with very high write endurance. This paper is an overview of MRAM design considerations. Topics covered include MRAM fundamentals, array architecture, several associated design studies, and scaling challenges. In addition, a 16-Mb MRAM demonstration vehicle is described, and performance results are presented.

A Study of Write Margin of Spin Torque Transfer Magnetic Random Access Memory Technology

Key design parameters of 64 Mb STT-MRAM at 90-nm technology node are discussed. A design point was developed with adequate TMR for fast read operation, enough energy barrier for data retention and against read disturbs, a write voltage satisfying the long term reliability against dielectric breakdown and a write bit error rate below 10-9. A direct experimental method was developed to determine the data retention lifetime that avoids the discrepancy in the energy barrier values obtained with spin current- and field-driven switching measurements. Other parameters detrimental to write margins such as backhopping and the existence of a low breakdown population are discussed. At low bit-error regime, new phenomenon emerges, suggestive of a bifurcation of switching modes. The dependence of the bifurcated switching threshold on write pulse width, operating temperature, junction dimensions and external field were studied. These show bifurcated switching to be strongly influenced by thermal fluctuation related to the spatially inhomogeneous free layer magnetization. An external field along easy axis direction assisting switching was shown to be effective for significantly reducing the percentage of MTJs showing bifurcated switching.

Fault-tolerant designs for 256 Mb DRAM

This paper describes fault-tolerant designs, which have been used to boost the yield of a 286 mm/sup 2/ 256 Mb DRAM with x32 both-ends DQ. The 256 Mb DRAM consists of sixteen 16 Mb units, each containing one 128 Kb row redundancy block. This row redundancy block architecture allows flexible row redundancy replacement, where random faults, clustered faults, and grouped faults can be efficiently repaired. Flexible column redundancy replacement with interchangeable master DQs (MDQ) is used to allow a 256 b data compression without causing a data conflict, while improving the column access speed by 2 ns. A depletion NMOS bitline-precharge-current-limiter suppresses the current flow which occurs as a result of a wordline-bitline short-circuit to only 15 /spl mu/A per cross fail, avoiding a standby current fail. Consequently, the hardware results show a significant yield enhancement of 16 times relative to the intra-block/segment replacement. Detailed simulation results show that this 256 Mb DRAM allows 275 random faults to be repaired with 5.5% silicon area overhead for 80% chip yield.

A 16Mb MRAM featuring bootstrapped write drivers

A 16Mb Magnetic Random Access Memory (MRAM) is demonstrated in 0.18 /spl mu/m three-Cu-level CMOS with a three-level MRAM process adder. The chip, the highest density MRAM reported to date, utilizes a 1.42 /spl mu/m/sup 2/ 1-Transistor 1-Magnetic Tunnel Junction (1T1MTJ) cell, measures 79mm/sup 2/ and features a /spl times/16 asynchronous SRAM-like interface. The paper describes the cell, architecture, and circuit techniques unique to multi-Mb MRAM design, including a novel bootstrapped write driver circuit. Hardware results are presented.

A high-speed 128 Kbit MRAM core for future universal memory applications

A 128 Kb MRAM (Magnetic Random Access Memory) test chip has been fabricated utilizing for the first time a 0.18 /spl mu/m, VDD=1.8 V, logic process technology with Cu backend of line. The presented design uses a 1.4 /spl mu/m/sup 2/ ITIMTJ (1-Transistor/1-Magnetic Tunnel Junction) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5 ns random array read access time and random write operations with <5 ns write pulse width.

Flexible test mode approach for 256-Mb DRAM

This paper describes a flexible test mode approach developed for a 256-Mb dynamic random access memory (DRAM). Test mode flexibility is achieved by breaking down complicated test mode control into more than one primitive test mode. The primitive test modes can be selected together through a WE CAS Before RAS (WCBR) cycle with a series of addresses for mode select. Although each primitive test mode may not complete a meaningful task alone, their combination performs many complex and powerful test modes. In this design, 64 primitive test modes are available. These can be combined to realize more than 19000 useful test modes. A new signal margin test mode is introduced which allows an accurate signal margin test even for small capacitance cells, which are difficult to identify in existing plate-bump method. A flexible multiwordline select test mode effectively performs a toggled wordline disturb test, a long t/sub RAS/ wordline disturb test, and a transfer gate stress voltage test, without causing any unnatural array disturbance. Finally, test modes, which can directly control the timing of sense amplifiers and column select lines, are discussed.

Flexible test mode design for DRAM characterization

Testing is a crucial process in the development and production of VLSI memory chips. On-chip test modes not only reduce manufacturing test time, but also allow effective debugging of the technology during the development phase. This paper describes the flexible test modes deployed in our fully functional 256 Mb DRAM chip.

A 286 mm/sup 2/ 256 Mb DRAM with /spl times/32 both-ends DQ

This paper describes a 256 Mb DRAM chip architecture which provides up to /spl times/32 wide organization. In order to minimize the die size, three new techniques: an exchangeable hierarchical data line structure, an irregular sense amp layout, and a split address bus with local redrive scheme in the both-ends DQ were introduced. A chip has been developed based on the architecture with 0.25 /spl mu/m CMOS technology. The chip measures 13.25 mm/spl times/21.55 mm, which is the smallest 256 Mb DRAM ever reported. A row address strobe (RAS) access time of 26 ns was obtained under 2.8 V power supply and 85/spl deg/C. In addition, a 100 MHz/spl times/32 page mode operation, namely 400 M byte/s data rate, in the standard extended data output (EDO) cycle has been successfully demonstrated.

A 220-mm/sup 2/, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture

A 220-mm/sup 2/, 256-Mb SDRAM has been fabricated in fully planarized 0.22-/spl mu/m CMOS technology with buried strap trench cell. The single-sided stitched word-line (WL) architecture employs asymmetric block activation and shared row decoders to realize 86.7% cell/chip-length efficiency (57.3% cell/chip efficiency). A staggered WL driver arrangement makes it possible to build the drivers on a 0.484-/spl mu/m WL pitch in limited space. An intraunit address increment pipeline scheme having two logical 8-Mb arrays within one physical 16-Mb unit results in a burst frequency up to 200 MHz for single data rate, while allowing four- and eight-bank organizations. A data rate of 270 Mbits/s was confirmed with a 135-MHz frequency doubling test mode. Single-ended addresses and a single ended read-write-drive bus reduce the ICC/sub 4/ current to /spl sim/90 mA for 100-MHz seamless burst operation. A detailed shmoo analysis demonstrates address-access time of 13.5 ns and clock-access time of 5 ns. This design also uses a selectable row domain and divided column redundancy scheme that repairs up to /spl sim/1400 faults/chip with only 8% chip overhead.