Damion Searls

A Method for Improving Component Decoupling Using Advanced Capacitor Under Ball Grid Array (ACUB)

Industry demands on power delivery continue to increase with higher performance silicon products. As a result, higher current sustainability and better transient response are key parameters frequently sought in successful power delivery designs. One key design feature for improved transient response involves locating decoupling capacitance as close to the load as possible. At the board level, this is typically accomplished by placing capacitors around the immediate vicinity of the load. With a set of identical capacitors in parallel, total capacitance is essentially a multiple of the number of caps while the effective series resistance and inductance is divided. However the realities of package and motherboard design can often limit the number and size of the capacitors placed in the vicinity of the load. In some cases, the capacitors may interfere with other routings to and from the component. In other cases, placement of the capacitors with respect to the DC current path may limit their effectiveness by inducing a large effective series inductance to the load. This paper describes a potential design method for maximizing capacitor effectiveness while minimizing its impact on other board features. The design is primarily implemented in board assembly and involves placing capacitors directly between power and ground board-component solder joints. As an extension of Capacitor Under BGA designs, this method is termed Advanced Capacitor Under BGA (ACUB). Using ACUB can improve load decoupling, but can require new approaches to board and component assembly. This paper discusses a number of potential design improvements allowed for using this design approach. In addition, factors involved in successful assembly are discussed and sets of proof-of-concept prototype designs are presented along with assembly results. From this, some designs with potential for further development are identified and next steps discussed.Copyright

Design and Assembly Methods for Improving High Current Board-Component Connectivity

Development of higher performance silicon products often leads to more stringent demands on power delivery. Higher current sustainability is often a key parameter in successful power delivery design. One potential bottleneck in the delivery of power to the component is the printed circuit board (PCB) to component interface. However in many designs, the same interconnect structure is used for both the power and signal connection even though the requirements for power and signaling can be different. For example in current art, a substantially similar solder ball and pad design is used for both power and signal connections. This results in interconnects that may not be optimized for high current power delivery, and in turn lead to unnecessarily high power loss at the interconnect. Under this design archetype, higher current generally requires more power/ground solder balls and thus larger packages. In addition, these power connections compete with much-needed IO connections on the component. This paper discusses methods for separating and optimizing the power and signal interconnect structures. Example proof-of-concept instances are given using different component/board layout patterns and surface mount technology (SMT) structures. For example, one of these instances involves increasing BGA solder density to the point where solder may gang together during board assembly reflow (a design called ganged solder). Another example involves varying the board pad and via layout pattern and depth to accompany optimized high current socket contacts. The data indicates that employing such separation and optimization techniques can lead to a substantial drop in board and interconnect resistance. In each case, voltage gradient, temperature and resistance data is collected, and relative performance trends are discussed.Copyright