Dudi Amir

Solder Joint Reliability Improvement Using the Cold Ball Pull Metrology

The various methods for improvement of package solder joint reliability (SJR) have centered on the broad categories of (i) reductions in the thermomechanical and mechanical stresses and strains applied to the joints, and (ii) strengthening of the solder interconnect interfaces and materials themselves. In practice, the success of the former depends first and foremost on the latter — an adequate and consistent interconnect ‘strength’ during the package development and production cycles. With the advancement of various pad-plating technologies (most notably ENIG – Electroless Nickel Immersion Gold), sphere chemistries, fluxes and processing conditions, each with their own stability issues, the interconnect strengths can easily undergo seemingly random drifts over time. The Dage™ Cold Ball Pull (CBP) technique, however, has emerged as an attractive alternative to the traditional ball-shear metrology as an interconnect strength monitor. The open issues preventing its adoption are related to identifying the best test conditions (e.g. aging time, pull speed, jaw pressure, etc...), all of which are addressed here. After identifying the best test conditions, we present a number of experimental results that highlight the powerful capability of this tool for optimizing and monitoring solder-joint strength. A full metrology characterization to demonstrate accuracy, repeatability and reproducibility has been performed. Moreover, interesting results have been obtained with respect to solder-aging, multiple-reflow, and time-above-liquidus effects on interconnect strength. Examples of direct correlation between CBP measurements and solder-joint shock performance are demonstrated. CBP is also shown to correlate well to other strength metrologies, such as three-point bend. Finally, CBP is used here to show how to strengthen interconnects by the proper selection of pad plating chemistries, sphere compositions, fluxes, reflow conditions, etc[[ellipsis]] Maintaining those strengths through development and production can be handled effectively using CBP as a monitor. Looking forward, CBP data presented here shows that certain material and processing choices can maximize lead-free solder interconnect strength and lead-free solder joint reliability.© 2005 ASME

Design and Assembly Methods for Improving High Current Board-Component Connectivity

Development of higher performance silicon products often leads to more stringent demands on power delivery. Higher current sustainability is often a key parameter in successful power delivery design. One potential bottleneck in the delivery of power to the component is the printed circuit board (PCB) to component interface. However in many designs, the same interconnect structure is used for both the power and signal connection even though the requirements for power and signaling can be different. For example in current art, a substantially similar solder ball and pad design is used for both power and signal connections. This results in interconnects that may not be optimized for high current power delivery, and in turn lead to unnecessarily high power loss at the interconnect. Under this design archetype, higher current generally requires more power/ground solder balls and thus larger packages. In addition, these power connections compete with much-needed IO connections on the component. This paper discusses methods for separating and optimizing the power and signal interconnect structures. Example proof-of-concept instances are given using different component/board layout patterns and surface mount technology (SMT) structures. For example, one of these instances involves increasing BGA solder density to the point where solder may gang together during board assembly reflow (a design called ganged solder). Another example involves varying the board pad and via layout pattern and depth to accompany optimized high current socket contacts. The data indicates that employing such separation and optimization techniques can lead to a substantial drop in board and interconnect resistance. In each case, voltage gradient, temperature and resistance data is collected, and relative performance trends are discussed.Copyright