Terry Dishongh

Thermomechanical behavior of micron scale solder joints under dynamic loads

Recent trends in reliability and fatigue life analysis of electronic devices have involved developing structural integrity models for predicting the operating lifetime under vibratory and thermal environmental exposure. Solder joint reliability is the most critical issue for the structural integrity of surface mounted electronics. Extensive research has been done on thermal behavior of solder joints, however, dynamic loading effects to solder joint fatigue life have not been thoroughly investigated. The physics of solder joint failure under vibration is still not very clear. This paper presents a test program which was performed to study inelastic behavior of solder joints of BGA packages. A concurrent loading unit is used which consists of a thermal environmental chamber and an electrodynamic shaker. Laser Moire Interferometry was used to measure the whole deformation field of the prepared specimen surface. The corresponding inelastic strain field is then calculated. It is found that at elevated temperature, vibration and shock can cause the accumulation of inelastic strains and damage in solder joints. In this paper, contrary to the popular belief that all vibration-induced strains are elastic, it is shown that vibration can cause significant inelastic strains.

Thermo-Mechanical Challenges in Stacked Packaging

The convergence of computing and communications dictates building up rather than out. As consumers demand more functionality in their hand-held devices, the need for more memory in a limited space is increasing, and integrating various functions into the same package is becoming more crucial. Over the past few years, die stacking has emerged as a powerful tool for satisfying these challenging integrated circuit (IC) packaging requirements. In this paper, a review of thermo-mechanical challenges for stacked die packaging is discussed.

Impact of temperature cycle profile on fatigue life of solder joints

In this paper the influence of the temperature cycle time history profile on the fatigue life of ball grid array (BGA) solder joints is studied. Temperature time history in a Pentium processor laptop computer was measured for a three-month period by means of thermocouples placed inside the computer. In addition, Pentium BGA packages were subjected to industry standard temperature cycles and also to in-situ measured temperature cycle profiles. Inelastic strain accumulation in each solder joint during thermal cycling was measured by high sensitivity Moire interferometry technique. Results indicate that fatigue life of the solder joint is not independent of the temperature cycle profile used. Industry standard temperature cycle profile leads to conservative fatigue life observations by underestimating the actual number of cycles to failure.

Inelastic behavior of microelectronics solder joints under concurrent vibration and thermal cycling

Concurrent vibration and thermal environment is commonly encountered in the service life of electronic packaging, such as automotive, airplane, military and mobile electronic devices. Solder joint reliability has been a critical issue of the overall design of microelectronic devices. However, the contribution of vibration to thermal fatigue life of solder joints has rarely been investigated. Vibration is taken as a loading case that only causes elastic material response. Literature is scarce on vibration plasticity and vibration caused fatigue. The standard practice in the industry is to use Miners rule to calculate combined environment fatigue life. This study shows that using Miners rule for fatigue life under combined loading is inaccurate. There are a number of models on thermomechanical behavior of solder joints, yet few models are verified by test data obtained from actual package size solder joints under realistic thermomechanical loading. The authors see the need of such tests for the purpose of better understanding of material behavior of solder joints under thermal and vibration loading and providing a solid basis for more accurate material modeling and fatigue life prediction. This paper reports observations from a series of concurrent thermal cycling and vibration tests on 63Sn/37Pb solder joints of an actual ball grid array (BGA) package. Moire interferometry (MI) is used to measure the inelastic deformation field of solder joints with submicron resolution, A large capacity Super AGREE thermal chamber and a high acceleration electrodynamic shaker is assembled together to perform the concurrent cycling. The cyclic plasticity of solder joints and microstructure evolution are discussed and related to fatigue life prediction.

Selecting a temperature time history for predicting fatigue life of microelectronics solder joints

Temperature cycling tests are standard industry practice for determining the thermomechanical fatigue life of solder joints. Industry-standard temperature profiles usually start from room temperature, then go to a high temperature, then to a cold temperature, and then back to room temperature. In addition, most of the time, the temperature profile contains dwell times at the highest and lowest temperatures. The dwell time at a high temperature corresponds to the on-state storage of the device, and the cold-temperature dwell time simulates the off-state storage of the device. In this study, the actual temperature history of a Ball Grid Array (BGA) package in a laptop computer was measured in situ. Experimental reliability studies were conducted using the in situ measured temperature history as well as industry-standard temperature history. This article presents the influence of temperature history on solder joint fatigue life. In order to measure deformations in the solder joint under cycling loading, a new Moire interferometry grating replication technique was developed to be able to measure strain field during fatigue testing.

The deployment of a non-intrusive alternative to sleep/wake wrist actigraphy in a home-based study of the elderly

This paper reports on experimental trials with an Under Mattress Bed Sensor (UMBS), an easily deployable, non-contact, low cost alternative to the actigraphy watch for sleep monitoring. Results from a home-based study of elderly subjects confirm accurate temporal resolution of activity monitoring in bed. UMBS activity classification thresholds were determined by maximizing Matthews Correlation Coefficient between the activity data captured using an actigraphy watch and the proposed sensor. Preliminary results on a healthy young subject showed very high agreement rates justifying its use as a replacement for wrist actigraphy.

Thermal management of die stacking architecture that includes memory and logic processor

The convergence of computing and communications dictates building up rather than out. As consumers demand more functions in their hand-held devices, the need for more memory in a limited space is increasing, and integrating various functions into the same package is becoming more crucial. Over the past few years, die stacking has emerged as a powerful tool for satisfying these challenging integrated circuit (IC) packaging requirements. Previously, present authors reported on the thermal challenges of various die stacking architectures that included memory (volatile and non-volatile) only. In this paper, the focus is on stacking memory and the logic processor on the same substrate. In present technologies, logic processor and memory packages are located side-by-side on the board or they are packaged separately and then stacked on top of each other (package-on-package [PoP]). Mixing memory and logic processor in the same stack has advantage and challenges, but requires the integration ability of economies-of-scale. Geometries needed were generated by using Pro/Engineerreg Wildfiretrade 2.0 as a computer-aided-design (CAD) tool and were transferred to ANSYSreg Workbenchtrade10.0, where meshed analysis was conducted. Package architectures evaluated were rotated stack, staggered stack utilizing redistributed pads, and stacking with spacers, while all other parameters were held constant. The values of these parameters were determined to give a junction temperature of 100degC, which is an unacceptable value due to wafer level electromigration. A discussion is presented in what parameters need to be adjusted in order to meet the required thermal design specification. In that light, a list of solutions consisting of increasing the heat transfer co-efficient on top of the package, the use of underfill, improved thermal conductivity of the PCB, and the use of a copper heat spreader were evaluated. Results were evaluated in the light of market segment requirements

Design for stackability of flash memory devices based on thermal optimization

Convergence of computing and communications dictates building up rather than out. As consumers demand more functions in their hand-held devices, the need for more memory in a limited space is increasing. Over the past few years, die stacking has emerged as a powerful tool for satisfying challenging IC packaging requirements. As stacked packaging evolves into taller stacks, what issues do we face? Traditionally, chip stacking was carried out with dies of different sizes so the top die was always smaller than the bottom die to permit wire bonding of both. Today, its common to see the stacking of same-size dies or a larger die over a smaller one. One way to accommodate a larger or same-size die on top is to place a spacer (a dummy piece of silicon) between the two. Then, the spacer lifts the top die just enough to allow wire bonding to the bottom die. Another way of stacking same size die is by placing the die in different orientation. This paper focuses on the thermal analysis and optimization of stacked die area array package. Thermal analysis was done on a 3-Die stacked FBGA package using FEM tool ANSYS 9.0. Optimization was then performed on a 3-Die stacked area array package using design explorer. Then the 3-Die stacked package was extended to 7-Die stacked package using ANSYS Workbench 9.0. Three different stack configurations (staggered, rotated and spacer die) with same die size were considered for comparison purposes. Optimization was done by varying seven die powers to get the best design for stackability based on thermal performance of the package.

Thermomechanical behavior of BGA solder joints under vibrations: an experimental observation

Recent trends in reliability and fatigue life analysis of electronic devices have involved developing structural integrity models for predicting the operating lifetime under vibratory and thermal environmental exposure. Solder joint reliability is the most critical issue for the structural integrity of surface mounted electronics. Extensive research has been done on thermal behavior of solder joints, however, dynamic loading effects on solder joint fatigue life have not been thoroughly investigated. The physics of solder joint failure under vibration is still not very clear. This paper presents a test program which was performed to study inelastic behavior of solder joints of BGA packages. A concurrent loading unit is used which consists of a thermal environmental chamber and an electrodynamic shaker. Laser Moire Interferometry was used to measure the whole deformation field of the prepared specimen surface. The corresponding inelastic strain field is then calculated. It is found that at elevated temperature, vibration and shock can cause the accumulation of inelastic strains and damage in solder joints. In this paper, contrary to the popular belief that all vibration-induced strains are elastic, it is shown that vibration can cause significant inelastic strains.

A Bluetooth-based minimum infrastructure home localisation system

Indoor location tracking is a function best suited to wireless LAN devices. This generally precludes it from home use in isolated rural areas, where WLAN is a rare commodity. We propose an affordable localisation system which can be implemented using a variety of Bluetooth enabled mobile phones. This permits the incorporation of cellular network signal measurements as well as Bluetooth link measurements into the localisation framework. This paper presents a Hidden Markov Model localisation method, utilising the Viterbi algorithm, which enables single Bluetooth access point localisation. The improvement of accuracy this presents over a Naive Bayes classifier is illustrated, along with the optimal method of obtaining training data.