Shuangqu Huang

An 847–955 Mb/s 342–397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13

This paper presents a partially-parallel dual-path fully-overlapped QC-LDPC decoder for the WiMAX system. By adopting five techniques including symmetrical six-stage pipelining, block column and row interleaving, nonzero sub-matrix reordering, sum memory quad-partition and read-write bypass, the decoder continuously scans nonzero sub-matrices two by two in the block row-wise order without any memory access conflict. Two phases are fully overlapped with each other, and the check node updating phase always takes the latest sums from the previous variable node updating phase. The sum memory stores not only the posterior sums but also the prior messages, which saves 11,520 memory bits. It only takes 48-54 clock cycles for the decoder to finish one iteration. The read-write accesses to sum memories are reduced by 24.3%-48.8%. Fabricated in the SMIC 0.13 μ m CMOS process, the decoder occupies 4.84 mm 2 with core area of 3.03 mm2, attains 847-955 Mb/s at 214 MHz and 10 iterations, and consumes 342-397 mW at 1.2 V with power efficiency of 39-46 pJ per bit per iteration.

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In this paper a programmable and area-efficient decoder architecture supporting two main stream decoding algorithms for any Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes. To verify our proposed architecture, a flexible LDPC decoder which supports IEEE 802.16e is implemented using a 0.13um CMOS process with a total area of 6.3 mm2 and maximum clock frequency of 260 MHz. The estimated comsumption is 270 mW when operates at 125 MHz and 1.2V supply.

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A fully-overlapped multi-mode QC-LDPC decoder architecture, adopting improved TDMP algorithm, is presented in this paper. With symmetrical four-stage pipelining, block column and row permutations, nonzero sub-matrix reordering, sum memory odd-even partition, and read-write bypass, two phases are fully overlapped and each phase scans nonzero sub-matrices one by one in block row-wise order without access conflicts to sum memories. The sum memories store not only variable node sums but also prior messages. In this case, it saves an additional FIFO of 13 440 bits. The decoder attains 248-287 Mb/s at 150 MHz and 15 iterations.

A flexible LDPC decoder architecture supporting two decoding algorithms

Based on the Min-Sum algorithm, this paper proposes an LDPC decoder integrating the TDMP schedule, which could achieve low complexity as well as good performance. The LDPC decoder is for DVB-S2, which includes 11 kinds of code rates with a block size of 64800. Based on SMIC 0.13µm standard CMOS process, the LDPC decoder has an estimation area of 14mm2, a throughput of 135Mbps with a frequency of 105MHz and maximum iteration number of 30,which shows advantage over previous DVB-S2 LDPC decoders1.

A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications

Since Low-Density Parity-Check codes have near-capacity decoding performance and very high decoding throughput, they have been employed as FEC coding scheme in many transmission standards for wireless communication, such as IEEE 802.22n, IEEE 802.16e, DVB-S2, and DTMB. This trend triggers the need for so-called multi-standard LDPC decoders. In this paper, a flexible architecture that supports multiple code rates, variable block sizes and is code independent for block-LDPC codes is proposed, based on rearranged TPMP algorithm,. By implementing a dynamically reconfigurable RPPU, our proposed architecture can be configured into row update or column update mode by time-division multiplexing. Consequently, the decoder achieves a high area and power efficiency. To verify our proposed architecture, a novel LDPC decoder which supports IEEE802.16e standard has been implemented. The results on a 0.18 um CMOS process show that the decoder occupies an area of approximately 13.7 mm2 and runs correctly at an maximum operating frequency of 110 MHz, resulting in 98 Mbps decoding throughput1.

A cost efficient LDPC decoder for DVB-S2

An important trend of the modern mobile device is that a single user terminal that will be capable of receiving signals of multiple different transmission standards. Most of these transmission standards employ a forward error correction decoding, including Reed-Solomon, Viterbi, Turbo and low-density parity check and so on. In this overview paper we review several programmable and area-efficient decoder architectures within one hardware platform. We show, in the case of guaranteed throughput performance, compared with multi-core implementation way, better power consumption performance can be gotten.

A flexible architecture for multi-standard LDPC decoders

This paper proposes a multi-mode solution that can be implemented in any applications requiring more than one RS code rate. We develop the Multi-Symbol Process Element (PE) in KES part to meet the multi-mode applications requirement and greatly reduce hardware complexity. The Multi-Symbol PE makes KES module simple and regular as well as area efficient. Besides, basic cells of Syndrome Calculation module and Error Correction module are grouped to meet the multi-mode goal. With the method we provided in this paper, a general solution for multi-mode system can be concluded. The synthesis results of VLSI structure under CMMB standard show that it costs only 73,408 gates by SMIC 0.13µm library. 1