Dan Niu

A sub-0.3V CMOS rectifier for energy harvesting applications

This paper presents a sub-0.3V CMOS full-wave rectifier for energy harvesting devices. By adopting a body-input comparator with simple bias circuit and body bias technique, the lowest input voltage amplitude can be reduced to 0.28V when using a standard CMOS 0.18µm process. The voltage drop of negative voltage converter can be reduced to enhance the output voltage by the body bias technique. In combination with the proposed comparator with minimum reverse current, the proposed active rectifier can achieve the peak voltage conversion efficiency of over 96 % and the maximum power efficiency near to 94 %.

A Two-stage CMOS Integrated Highly Efficient Rectifier for Vibration Energy Harvesting Applications

We report, in this paper, a highly efficient CMOS rectifier for low power energy harvesting system. By using two-stage structure and a novel active diode, the rectifier can work at a wide range of input voltage amplitudes of 0.45V up to 1.8V under a standard 0.18um CMOS process. A comparator that consists of common-gate stage and control stage is designed to control the switch of the active diode. The proposed rectifier can achieve a peak voltage conversion efficiency of over 96% and a power efficiency over 90%. Simulated power consumption of the rectifier is 197nW at 450mV, which is about 30% smaller than the best recently published results.

The limitation for the growth of step of DPTA method

The damped pseudo-transient analysis (DPTA) method, of step 1 up to 3 are described as they are applied to a nonlinear circuit. The DPTA method with an effective implementation based on SPICE3 is compared to the pure pseudo-transient analysis and compound element pseudo-transient analysis (CEPTA) methods, and is shown to be more efficient. The first order multi-step linear integration algorithms, k step damped differentiation formulas (DDF-k), are applied to the DPTA method. For timestep Δt fixed, the damping effect of DPTA methods is enlarged as k increases. In this paper, we analyze the features for different step k. Also the limitation and how to choose suitable value for the step k are discussed.