Zhangcai Huang

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

With the scaling of complementary metal-oxide-semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

A low voltage CMOS rectifier for wirelessly powered devices

This paper presents a low voltage CMOS full-wave rectifier for wirelessly powered devices. By using a simple comparator-controlled switch, the lowest input voltage amplitude can be reduced to 0.7V when using a standard CMOS 0.18μm process. With only one comparator, the proposed design dramatically reduces the production cost. In combination with unbalanced transistor scale, the proposed rectifier can achieve a maximum peak voltage conversion efficiency of more than 93% and power efficiency near to 87%.

A CMOS Sub-l-V nanopower current and voltage reference with leakage compensation

In this paper, a CMOS sub-1-V nanopower reference is proposed, which is implemented without resistors and with only standard CMOS transistors. The proposed circuit has the most attractive merit that it can afford reference current and reference voltage simultaneously. Moreover, the leakage compensation technique is utilized, and thus it has very low temperature coefficient for a wide temperature range. The proposed circuit is verified by SPICE simulation with CMOS 0.18um process. The temperature coefficient of the reference voltage and reference current are 0.0037%/°C and 0.0091%/°C, respectively. Also, the power supply voltage can be as low as 0.85V and its power consumption is only 5.1nW.

High efficiency four-phase All PMOS charge pump without body effects

In this paper, a four-phase all PMOS charge pump based on the voltage doubler structure is proposed. The proposed charge pump is designed in 1.8 V 0.18 mum standard CMOS process with high voltage boosting efficiency and little output ripple. Moreover, it solves the voltage overstress problem which exists in the conventional charge pump and eliminates the body effect as well by means of adding two auxiliary substrate switching PMOS transistors. The simulation results show that the proposed charge pump circuits have an improvement about 93.2% compared with the original two-phase Dickson charge pump and an improvement about 28.2% compared with the negative four-phase Dickson charge pump when the supply voltage is 1.8 V. Moreover it can even work as long as the supply power voltage is larger than the threshold voltage, which makes it quite suitable to be utilized in low supply voltage applications.

Behavioral Circuit Macromodeling and Analog LSI Implementation for Automobile Engine Intake System

Accurate estimating or measuring the intake manifold absolute pressure plays an important role in automobile engine control. In order to achieve the real-time estimation of the absolute pressure, the high accuracy and high speed processing ability are required for automobile engine control systems. Therefore, in this paper, an analog method is discussed and a fully integrated analog circuit is proposed to simulate automobile intake systems. Furthermore, a novel behavioral macromodeling is proposed for the analog circuit design. With the analog circuit, the intake manifold absolute pressure, which plays an important role for the effective automobile engine control, can be accurately estimated or measured in real time.

Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies

With the scaling of CMOS technology, the overshooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results.

A low breakdown-voltage charge pump based on Cockcroft-Walton structure

A Cockcroft-Walton type charge pump circuit is proposed in this paper. Compared with Dickson type, each transistor and capacitor in the proposed circuit just stand against the voltage less than one Vdd, so that a low break-down voltage process can be applied to this kind of charge pump to reduce the chip area cost and break-down risk. By using the proposed structure, the performances of voltage boosting efficiency and power efficiency can reach 98.9% and 87%.

An Effective Pseudo-Transient Algorithm for Finding DC Solutions of Nonlinear Circuits

The pseudo-transient method is discussed in this paper as one of practical methods to find DC operating points of nonlinear circuits when the Newton-Raphson method fails. The mathematical description for this method is presented and an effective pseudo-transient algorithm utilizing compound pseudo-elements is proposed. Numerical examples are demonstrated to prove that our algorithm is able to avoid the oscillation problems effectively and also improve the simulation efficiency.

A Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback

A new circuit structure for a CMOS four-quadrant analog multiplier is presented. In this circuit, the active feedback technique is used to obtain high linearity and wide input dynamic range. The simulation results show that the proposed multiplier can offer plusmn1.8V input dynamic range for a plusmn2.5V supply voltage, which is much larger than the conventional CMOS analog multipliers

Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew

In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect loads. Many Ceff algorithms have been proposed to compute gate delay of interconnect loads. However, less work has been done to develop a Ceff algorithm which can accurately predict gate slew. In this paper, we propose a novel method for calculating the Ceff of interconnect load for gate slew. We firstly establish a new expression for Ceff in 0.8Vdd point. Then the Integration Approximation method is used to calculate the value of Ceff in 0.8Vdd point. In this method, the integration of a complicated nonlinear gate output is approximated with that of a piecewise linear waveform. Based on the value of Ceff in 0.8Vdd point, Ceff of interconnect load for gate slew is obtained. The simulation results demonstrate a significant improvement in accuracy.