Minglu Jiang

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

With the scaling of complementary metal-oxide-semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

High efficiency four-phase All PMOS charge pump without body effects

In this paper, a four-phase all PMOS charge pump based on the voltage doubler structure is proposed. The proposed charge pump is designed in 1.8 V 0.18 mum standard CMOS process with high voltage boosting efficiency and little output ripple. Moreover, it solves the voltage overstress problem which exists in the conventional charge pump and eliminates the body effect as well by means of adding two auxiliary substrate switching PMOS transistors. The simulation results show that the proposed charge pump circuits have an improvement about 93.2% compared with the original two-phase Dickson charge pump and an improvement about 28.2% compared with the negative four-phase Dickson charge pump when the supply voltage is 1.8 V. Moreover it can even work as long as the supply power voltage is larger than the threshold voltage, which makes it quite suitable to be utilized in low supply voltage applications.

A sub-0.3V CMOS rectifier for energy harvesting applications

This paper presents a sub-0.3V CMOS full-wave rectifier for energy harvesting devices. By adopting a body-input comparator with simple bias circuit and body bias technique, the lowest input voltage amplitude can be reduced to 0.28V when using a standard CMOS 0.18µm process. The voltage drop of negative voltage converter can be reduced to enhance the output voltage by the body bias technique. In combination with the proposed comparator with minimum reverse current, the proposed active rectifier can achieve the peak voltage conversion efficiency of over 96 % and the maximum power efficiency near to 94 %.

MODELING THE OVERSHOOTING EFFECT OF MULTI-INPUT GATE IN NANOMETER TECHNOLOGIES

With the advent of nanometer age in digital circuits, the overshooting time becomes a dominating component of gate delay for CMOS logic gates. Till now, few researches have focused on the overshooting effect of multi-input gate. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.

An advanced model for calculating the effective capacitance considering input waveform effect

In deep submicron designs, predicting gate delays is a noteworthy work for static timing analysis (STA). The effective capacitance Ceff concept is usually used to calculate the gate delay of interconnect load. Conventionally, the input-signal is assumed as ramp waveform. However, the input waveform is also the output of CMOS gates with interconnect wires. Thus the simple assumption as a ramp signal results in significant influence on the delay calculating. In this paper, an advanced effective capacitance model is proposed to consider both the input waveform effect and interconnect wire load, where the nonlinear influence of input waveform is modeled as one part of effective capacitance of capacitive load to compute the gate delay. Experimental results show a significant improvement in accuracy when the input waveform effect is considered.

Modeling the overshooting effect of multi-input gate in nanometer technologies

With the advent of nanometer age in digital circuits, the overshooting time becomes a dominating component of gate delay for CMOS logic gates. Till now, few researches have focused on the overshooting effect of multi-input gate. Therefore, in this paper, an effective model considering the overshooting effect of multi-input gate is presented. The experimental results using 32nm PTM model reflect that the proposed model is accurate within 3.6% error compared with SPICE simulation results.

A non-iterative effective capacitance model for CMOS gate delay computing

In Static Timing Analysis, the conventional methods usually use an iterative method to ensure the accuracy of the effective capacitance Ceff, which is usually used to compute the delay of gate with interconnect load and to capture the output signal shape of the real gate response. In this paper, a polynomial approximation method is used to make the nonlinear Ceff equation be solved without iterative method. Compared to the conventional methods, the proposed method has the merit of improving the efficiency for Ceff calculation. Meanwhile, experimental results show that the proposed method is in agreement with the Spice simulation.