Daniel González

The master-slave paradigm on heterogeneous systems: a dynamic programming approach for the optimal mapping

We study the master-slave paradigm over heterogeneous systems. According to an analytical model, we develop a dynamic programming algorithm that allows to solve the optimal mapping for such paradigm. Our proposal considers heterogeneity due both to computation and also to communication. The optimization strategy used allows us to obtain the set of processors for an optimal computation. The computational results show that considering heterogeneity also on the communication increases the performance of the parallel algorithm.

On the prediction of master-slave algorithms over heterogeneous clusters

We study the performance of master-slave algorithms on heterogeneous networks. The word heterogeneity refers here to both the processing and communication capabilities. Following an inductive approach, we derive a formula that predicts the performance for the general case. The computational results carried out on a heterogeneous cluster of PCs prove the effectiveness of the approach and the accuracy of the predictions. The numerical minimization of this function provides an efficient approach for an optimal distribution of the work.

An Analytical Model for Pipeline Algorithms on Heterogeneous Clusters

The performance of a large class of virtual pipeline algorithms on heterogeneous networks is studied. The word heterogeneity refers here both to the processing and communication capabilities. To balance the differences among processors requires a vectorial combination of block and cyclic mappings, assigning different number of virtual processes per processor. Following a progressive approach, we derive a formula that predicts the performance for the general case. The computational results carried out on a heterogeneous cluster of PCs prove the effectiveness of the approach and the accuracy of the predictions.

A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems

Synchronization of VLSI systems is growing in complexity because of the increase in die size and integration levels, along with stronger requirements for integrated circuit speed and reliability. The size increase leads to delays and synchronization losses in clock distribution. Additionally, the large amount of synchronous hardware in integrated circuits requires large current spikes to be drawn from the power supply when the clock changes state. This paper presents a new approach for clock distribution in RNS-based systems, where channel independence removes clock timing restrictions. This approach generates several clock signals with non-overlapping edges from a global clock. This technique shows a significant decrease in instantaneous current requirements and a homogeneous time distribution of current supply to the chip, while keeping extra hardware to a minimum and introducing an affordable power cost, as shown through simulation.

Protection of microprocessor-based cores for FPL devices

Microprocessor cores are widely used in the development of complex digital systems. In this paper, a new scheme for the IP protection of microprocessor cores is presented. The proposed framework can perform this task in two ways: the hosting of a digital signature using watermarking techniques that allows claiming authorship rights; and the introduction of additional hardware limiting the functionality of the core if it is not activated. This last feature enables the distribution of cores in “demo” mode. The protection method, named μIPP@HDL provides a robust protection system, while maintaining low overhead and a reasonable area increase, as experimental results show.

HIGH LEVEL PARALLEL SKELETONS FOR DYNAMIC PROGRAMMING

Dynamic Programming is an important problem-solving technique used for solving a wide variety of optimization problems. Dynamic Programming programs are commonly designed as individual applications and software tools are usually tailored to specific classes of recurrences and methodologies. That contrasts with some other algorithmic techniques where a single generic program may solve all the instances. We have developed a general skeleton tool providing support for a wide range of dynamic programming methodologies on different parallel architectures. Genericity, flexibility and efficiency are basic issues of the design strategy. Parallelism is supplied to the user in a transparent manner through a common sequential interface. A set of test problems representative of different classes of Dynamic Programming formulations has been used to validate our skeleton on an IBM-SP.

Efficient clock distribution scheme for VLSI RNS-Enabled controllers

Clock distribution has become an increasingly challenging problem for VLSI designs because of the increase in die size and integration levels, along with stronger requirements for integrated circuit speed and reliability. Additionally, the great amount of synchronous hardware in integrated circuits makes current requirements to be very large at very precise instants. This paper presents a new approach for clock distribution in PID controllers based on RNS, where channel independence removes clock timing restrictions. This approach generates several clock signals with non-overlapping edges from a global clock. The resulting VLSI RNS-enabled PID controller, shows a significant decrease in current requirements (the maximum current spike is reduced to a 14% of single clock distribution one at 125 Mhz) and a homogeneous time distribution of current supply to the chip, while keeping extra hardware and power to a minimum.