Daniel Magalotti

A Pattern Recognition Mezzanine based on Associative Memory and FPGA technology for Level 1 Track Triggers for the HL-LHC upgrade

The increment of luminosity at HL-LHC will require the introduction of tracker information at Level-1 trigger system for the experiments in order to maintain an acceptable trigger rate for selecting interesting events despite the one order of increased magnitude in the minimum bias interactions. In order to extract the track information in the required latency (~ 5–10 μ s depending on the experiment), a dedicated hardware processor needs to be used. We here propose a prototype system (Pattern Recognition Mezzanine) as core of pattern recognition and track fitting for HL-LHC experiments, combining the power of both Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices.

ATLAS FTK: Fast Track Trigger

A track reconstruction system for the trigger of the ATLAS detector at the Large Hadron Collider is described. The Fast Tracker is a highly parallel hardware system designed to operate at the Level-1 trigger output rate. It will provide high-quality tracks reconstructed over the entire inner detector by the start of processing in the Level-2 trigger. The system is based on associative memories for pattern recognition and fast FPGA’s for track reconstruction. Its design and expected performance under instantaneous luminosities up to 3 10 34 =cm 2 =s are discussed.

FTK: a Fast Track Trigger for ATLAS

We describe the design and expected performance of a the Fast Tracker Trigger (FTK) system for the ATLAS detector at the Large Hadron Collider. The FTK is a highly parallel hardware system designed to operate at the Level 1 trigger output rate. It is designed to provide global tracks reconstructed in the inner detector with resolution comparable to the full offline reconstruction as input of the Level 2 trigger processing. The hardware system is based on associative memories for pattern recognition and fast FPGAs for track reconstruction. The FTK is expected to dramatically improve the performance of track based isolation and b-tagging with little to no dependencies of pile-up interactions.

A two-tier monolithically stacked CMOS Active Pixel Sensor to measure charged particle direction

In this work we present an innovative approach to particle tracking based on CMOS Active Pixel Sensors (APS) layers, monolithically integrated in an all-in-one chip featuring multiple, stacked, fully functional detector layers capable to provide momentum measurement (particle direction) within a single detector by using multiple layer impact point coordinates. The whole system will results in a very low material detector, since each layer can be thinned down to tens of micrometres, thus dramatically reducing multiple scattering issues. To build such a detector, we rely on the capabilities of the CMOS vertical scale integration (3D-IC) 130 nm Chartered/Tezzaron technology, used to integrate two fully-functional CMOS APS matrix detectors, including both sensing area and control/signal elaboration circuitry, stacked in a monolithic device by means of Through Silicon Via (TSV) connections. Such a detector would allow accurate estimation of the impact point of an ionizing particle and of its incidence angle. Two batches of the first chip prototype have been produced and characterized using particle beams (e.g. protons) demonstrating the suitability of particle direction measurement with a single, multiple layers, 3D vertically stacked APS CMOS detector.

A Real-Time Demonstrator for Track Reconstruction in the CMS L1 Track-Trigger System Based on Custom Associative Memories and High-Performance FPGAs

A Real-Time demonstrator based on the ATCA Pulsar-IIB custom board and on the Pattern Recognition Mezzanine (PRM) board has been developed as a flexible platform to test and characterize low-latency algorithms for track reconstruction and L1 Trigger generation in future High Energy Physics experiments. The demonstrator has been extensively used to test and characterize the Track-Trigger algorithms and architecture based on the use of the Associative Memory ASICs and of the PRM cards. The flexibility of the demonstrator makes it suitable to explore other solutions fully based on high-performance FPGA device.

Track finding mezzanine for Level-1 triggering in HL-LHC experiments

The increase of the luminosity in the High Luminosity upgrade of the CERN Large Hadron Collider (HL-LHC) will require the use of Tracker information in the evaluation of the Level-1 trigger in order to keep the trigger rate acceptable (i.e.: <1MHz). In order to extract the track information within the latency constraints (<5µs), a custom real-time system is necessary. We developed a prototype of the main building block of this system, the Pattern Recognition Mezzanine (PRM) that combines custom Associative Memory ASICs with modern FPGA devices. The architecture, functionality and test results of the PRM are described in the present work.

Track finding based on Associative Memories for Level-1 triggering in HL-LHC experiments

The increase of the luminosity in the High Luminosity upgrade of the CERN Large Hadron Collider (HL-LHC) will require the use of Tracker information in the evaluation of the Level-1 trigger in order to keep the trigger rate acceptable (i.e.: <; 1MHz). A custom real-time system will be needed to extract the track information within the latency constraints (<;10usec). We developed the prototype of the building block of this system, the Pattern Recognition Mezzanine (PRM) that combines the power of both Associative Memory custom ASICs and modern FPGA devices. The architecture and the functionalities of the PRM are described here.

The Associative Memory system for the FTK processor at ATLAS

Ricardo Ciprianiab, Saverio Citraro∗ab, Simone Donatiab, Paola Giannettib, Agostino Lanzac, Pierluigi Lucianoab, Daniel Magalottid , Marco Piendibeneab. aUniversity of Pisa, Largo B. Pontecorvo, 3 56127 Pisa, Italy bSezione di Pisa INFN, Largo Bruno Pontecorvo 3, 56127 Pisa, Italy cSezione di Pavia INFN, Via Agostino Bassi, 6 27100 Pavia, Italy dUniversity of Modena and Reggio Emilia, Via Universita’ 4, 41121 Modena, Italy E-mail: r.cipriani@studenti.unipi.it, saverio.citraro@pi.infn.it, simone.donati@pi.infn.it, paola.giannetti@pi.infn.it, agostino.lanza@pv.infn.it, p.luciano@studenti.unipi.it, daniel.magalotti@pg.infn.it, marco.piendibene@pi.infn.it

3D monolithically stacked CMOS Active Pixel Sensors for particle position and direction measurements

In this work we propose a 3D monolithically stacked, multi-layer detectors based on CMOS Active Pixel Sensors (APS) layers which allows at the same time accurate estimation of the impact point and of the incidence angle an ionizing particle. The whole system features two fully-functional CMOS APS matrix detectors, including both sensing area and control/signal elaboration circuitry, stacked in a monolithic device by means of Through Silicon Via (TSV) connections thanks to the capabilities of the CMOS vertical scale integration (3D-IC) 130 nm Chartered/Tezzaron technology. In order to evaluate the suitability of the two layer monolithic active pixel sensor system to reconstruct particle tracks, tests with proton beams have been carried out at the INFN LABEC laboratories in Florence (Italy) with 3 MeV proton beam.