Francesco Crescioli

Next generation associative memory devices for the FTK tracking processor of the ATLAS experiment

Higher LHC energy and luminosity increase the challenge of track reconstruction for the ATLAS trigger. To effectively handle the very high data rate, a dedicated hardware-based system has been designed. The Fast Track Trigger (FTK) will provide high quality track reconstruction over the entire detector volume to be run after the first level trigger has accepted an event. It will help to improve the efficiency and background rejection for triggers on tau leptons and b-hadrons by the second level trigger and help reduce the luminosity dependence of isolation requirements for electrons and muons. In this paper we present the status of associative memory design and its future development.

Characterisation of an Associative Memory Chip for high-energy physics experiments

This paper presents the approach used to characterize an Associative Memory Chip (AMChip) designed for the trigger systems of high-energy physics experiments in the Large Hadron Collider (LHC) at CERN. Pattern recognition is performed with Associative Memories (AM). A dedicated integrated circuit has been designed, fabricated and tested to verify that the proposed solution meets area, speed and current consumption requirements.

The Associative Memory Serial Link Processor for the Fast TracKer (FTK) at ATLAS

The Fast TracKer (FTK) is an extremely powerful and very compact processing unit, essential for efficient Level 2 trigger selection in future high-energy physics experiments at the LHC. FTK employs Associative Memories (AM) to perform pattern recognition; input and output data are transmitted over serial links at 2 Gbit/s to reduce routing congestion at the board level. Prototypes of the AM chip and of the AM board have been manufactured and tested, in preparation of the imminent design of the final version.

Performance of the AMBFTK board for the FastTracker processor for the ATLAS detector upgrade

Modern experiments at hadron colliders search for extremely rare processes hidden in a very large background. As the experiment complexity and the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. The FastTracker (FTK) processor for the ATLAS experiment offers extremely powerful, very compact and low power consumption processing units for the future, which is essential for increased efficiency and purity in the Level 2 trigger selection through the intensive use of tracking. Pattern recognition is performed with Associative Memories (AM). The AMBFTK board and the AMchip04 integrated circuit have been designed specifically for this purpose. We report on the preliminary test results of the first prototypes of the AMBFTK board and of the AMchip04.

Performance of the Proposed Fast Track Processor for Rare Decays at the ATLAS Experiment

The Fast Track processor (FTK) has been proposed for high-quality track finding at very high rates (Level-1 output rates) for the LHC experiments. Fast, efficient and precise pattern recognition has been studied using a silicon 7-layer sub-detector, including a subset of the pixel and SCT layers. We tested the FTK algorithms using the ATLAS full simulation. We compare the FTK reconstruction quality with the tracking capability of the offline iPatRec algorithm. We show that similar resolutions and efficiencies are reached by FTK at a speed higher than iPatRec by orders of magnitude. With FTK full events are reconstructed at the Level-1 output rate. Bo s rarr mu + mu- events are fufly simuiated together with background samples. We show that a low Level-2 rate is allowed by FTK, even using a singie 6 GeV Level-1 muon selection trigger. FTK provides the full-resolution track list ready for the Level-2 BBo s identification. All selection cuts performed by the Event Filter can be easily anticipated at Level-2. We present the Bo s rarr mu + mu- efficiency gain and related Level-2 rates.

Study of dosimetric observables to be used in Active Pixel Sensor based devices for Interventional Radiology applications

Interventional radiologists and staff members, during all their professional activities, are frequently exposed to protracted low doses of ionizing radiation. The authors present a novel approach to perform on line monitoring of the staff during interventional procedures by using a device based on a CMOS Active Pixel Sensor (APS). The sensor performance as an X-ray radiation detector has been evaluated with a dedicated experimental set-up and dosimetric observables have been assessed from the frames acquired by the sensor using a purposely designed algorithm. A data reduction strategy has also been implemented without significant loss of the performances. Finally a linear correlation with dosimetric measurements made using TLDs has been verified.

Next generation Associative Memory devices for the FTK tracking processor of the ATLAS experiment

The AMchip is a VLSI device that implements the Associative Memory function, a special content addressable memory specifically designed for high energy physics applications and first used in the CDF experiment at Tevatron. The 4th generation of AMchip has been developed for the core pattern recognition stage of the Fast TracKer (FTK) processor: a hardware processor for online reconstruction of particle trajectories at the ATLAS experiment at LHC. We present the architecture, design considerations, power consumption and performance measurements of the 4th generation of AMchip. We present also the design innovations toward the 5th generation and the first prototype results.

A Pattern Recognition Mezzanine based on Associative Memory and FPGA technology for Level 1 Track Triggers for the HL-LHC upgrade

The increment of luminosity at HL-LHC will require the introduction of tracker information at Level-1 trigger system for the experiments in order to maintain an acceptable trigger rate for selecting interesting events despite the one order of increased magnitude in the minimum bias interactions. In order to extract the track information in the required latency (~ 5–10 μ s depending on the experiment), a dedicated hardware processor needs to be used. We here propose a prototype system (Pattern Recognition Mezzanine) as core of pattern recognition and track fitting for HL-LHC experiments, combining the power of both Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices.

Heterogeneous computing system platform for high-performance pattern recognition applications

we present a system architecture made of a motherboard with a Xilinx Zynq System on Chip (SoC) and a mezzanine board equipped with an Associative Memory chip (AM). The proposed architecture is designed to serve as an accelerator of general purpose algorithms based on pipeline processing and pattern recognition. We present the open source software and firmware developed to fully exploit the available communication channels between the ARM CPU and the FPGA using Direct Memory Access (DMA) technique and the AM using Multi-Gigabit Transceivers (MGT). We report the measured performances and discuss potential applications and future developments. The proposed architecture is compact, portable and provide a large communication bandwidth between components.

Track finding mezzanine for Level-1 triggering in HL-LHC experiments

The increase of the luminosity in the High Luminosity upgrade of the CERN Large Hadron Collider (HL-LHC) will require the use of Tracker information in the evaluation of the Level-1 trigger in order to keep the trigger rate acceptable (i.e.: <1MHz). In order to extract the track information within the latency constraints (<5µs), a custom real-time system is necessary. We developed a prototype of the main building block of this system, the Pattern Recognition Mezzanine (PRM) that combines custom Associative Memory ASICs with modern FPGA devices. The architecture, functionality and test results of the PRM are described in the present work.