Daniel Séverac

A 1V RF SoC with an 863-to-928MHz 400kb/s radio and a 32b Dual-MAC DSP core for Wireless Sensor and Body Networks

A 150¿A/MHz DSP with two MAC/cycle instructions is integrated with a configurable 863-to-928MHz RF transceiver that yields 3.5mW in continuous reception, 2¿C per channel sampling and 40mW for 10dBm output. The SoC includes voltage converters that allow 1.0-to-1.8V or 2.7-to-3.6V primary voltage supplies. In sleep mode, it consumes 1¿A with a 32kHz crystal-based RTC running.

Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation

Planar bulk CMOS in subthreshold operation allows an important reduction of the power consumption. This can lead the way to new ultra low-power applications with autonomous devices supplied by energy harvesting techniques. However, subthreshold circuits are more sensitive to threshold voltage variations and require new layout optimizations. We propose a methodology to design robust standard cell circuits to cope with the challenges of reducing the supply voltage. We provide evaluations in the 180 nm technology node for area, power, timing and sensitivity to variations for a frequency division chain circuit - commonly used in watches - and for an ultra low-power 32-bit processor. The circuits developed with our subthreshold standard cell library are supplied at 0.4 V and can also work at 1.0 V, allowing multiple modes of operation for power management. We compare them to the same designs using a mature low-power library supplied at 1.0 V.

Cost-effective and miniaturized System-on-Chip based solutions for portable medical & BAN applications

A System-on-Chip (SoC) offers an optimal implementation of electronics for portable medical systems and in particular for Body Area Network (BAN) applications. It integrates as much functionality as possible into a single chip thereby allowing miniaturization of the system, while optimizing performance and power consumption. Using todays mature and cost effective semiconductor process CMOS technology platforms, the SoC based solutions also allow to optimize the cost and reliability of the overall system by reducing the bill of materials (BOM).

Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation

A 32-bit icyflex2 processor operating over a wide supply range (WSR) is presented, showing a very low energy consumption in comparison to other state-of-art 32-bit processors. Operating under very different supply conditions involves tremendous differences in operating frequency, and a large sensitivity to process and temperature variations at low-voltage, which both tend to complicate timing closure. In this paper, WSR is achieved on the one hand thanks to standard cells, RAM, ROM and level shifters optimized for sub-threshold operation and for low-leakage, and on the other hand thanks to a latch-based design methodology, which simplifies the timing closure in fast corners, while focusing on setup optimization in slow corners. Results are reported for the integration of this sub-threshold latch-based 32-bit icyflex2 processor in EM Microelectronic Marin ALP CMOS 180 nm technology showing full functionality for supply voltage ranging from 0.37 V (i.e. sub-threshold operation) to 1.8 V (i.e super-threshold operation), over 5 process corners and for temperatures between -25 and 75°C. The Minimum Energy Point (MEP), where the circuit operates at the highest energy efficiency, occurs at sub-threshold voltages, reaching an energy per operation as low as 17.1 pJ/cycle at 19 kHz and 0.37 V. The energy per operation rises to 119.3 pJ/cycle at 1.1 V and 10 MHz, almost 7 times higher than at the MEP, demonstrating the clear advantage of sub-threshold operation in terms of energy. This possibility to maintain continuous full functionality of the design by adapting the operation frequency and varying the supply voltage makes that design a perfect candidate for adaptive dynamic voltage frequency scaling (ADVFS).

Low-Power Heterogeneous Systems-on-Chips

The design of heterogeneous Systems-on-Chips (SoC) in very deep submicron technologies becomes a very complex task that has to bridge very high level system description with low-level considerations due to technology defaults and variations and increasing system and circuit complexity. This paper describes the major low-level issues, such as dynamic and static power consumption, temperature, technology variations, interconnect, DFM, reliability and yield, and their impact on high-level design, such as the design of multi-V dd , fault-tolerant, redundant or adaptive chip architectures. Some multi-processor based SoC (MPSoC) cases are also presented in three domains in which heterogeneity is large: wireless sensor networks, vision sensors and mobile TV. These examples also highlight the heterogeneous nature and the increasing complexity at circuit-level, with the extension from CMOS-only SoCs towards MEMS-and-CMOS SoCs.

A 32 kHz DTCXO RTC Module with an Overall Accuracy of ±1 ppm and an All-Digital 0.1 ppm Compensation-Resolution Scheme

This paper presents an ultralow power (240 nA), wide voltage range (1.25–5.5 V), temperature-compensated RTC module achieving a typical accuracy of ±1 ppm at 1 Hz over the industrial temperature range of −40 to 85 °C. This is obtained by combining a miniature tuning fork 32 kHz XTALs with an ASIC in a miniature 8-pin ceramic package measuring only 3.2×1.5×0.8 mm3. An innovative patented all-digital interpolation scheme allows the accurate generation of a one pulse per second (1 PPS) signal with a resolution of 0.1 ppm permitting significant savings in terms of both the circuit area and power consumption (4×) compared to previously available such products.

11.5 A 3.2×1.5×0.8mm3 240nA 1.25-to-5.5V 32kHz-DTCXO RTC module with an overall accuracy of µ1ppm and an all-digital 0.1ppm compensation-resolution scheme at 1Hz

Timekeeping based on a 32kHz XTAL still remains the most popular, cost effective, low power, accurate solution for low-power portable applications. Simple solutions with overall accuracies of a few 100ppm are based on the combination of a through-hole or SMD XTAL together with an oscillator implemented as part of the application SoC (micro-controller, cell phone). As a single-ppm error represents a deviation of 30s/year (nearly 1 hour/year at 100ppm!), temperature-compensated XTAL or MEMS oscillators (TCXO, TCMO) used for time-keeping applications have received significant research attention over the last decade, driven by further miniaturization, tighter accuracy and lower power consumption needs [1-4]. Combining both resonator and oscillator intimately or even better, in a single package, leads to superior stability, improved robustness and lower consumption by minimizing environmental effects (moisture, temperature gradients) and stray capacitance. Real-time clock (RTC) modules integrating further time, timer, calendar, time stamping and alarm functions have become a key power-management block capable of scheduling precise wake-up at user- or pre-defined intervals so that a more complex, energy-constrained application can be heavily duty-cycled and left mostly hibernating (e.g., wireless sensor node). They are found in a variety of consumer, metering, medical, wearable, automotive, communication, outdoor, safety, and automation applications, and are a key component of the upcoming IoE revolution.

Sub-Threshold Design and Architectural Choices

Standard cell design and memory design need to be optimized for sub-threshold operation. It is interesting to revisit digital block architectures when implemented using these sub-threshold basic bricks. Out of many possible architectures for the same logic function (i.e. Multiplier), it turns out that there are optimal sub-threshold architectures.