Nicola Scolari

A 1V RF SoC with an 863-to-928MHz 400kb/s radio and a 32b Dual-MAC DSP core for Wireless Sensor and Body Networks

A 150¿A/MHz DSP with two MAC/cycle instructions is integrated with a configurable 863-to-928MHz RF transceiver that yields 3.5mW in continuous reception, 2¿C per channel sampling and 40mW for 10dBm output. The SoC includes voltage converters that allow 1.0-to-1.8V or 2.7-to-3.6V primary voltage supplies. In sleep mode, it consumes 1¿A with a 32kHz crystal-based RTC running.

Ultra low-power MEMS-based radio for wireless sensor networks

The recent advances made in MEMS and particularly in RF MEMS technology are enabling new architectures for the integration of RF transceivers with improved performance and smaller size. Several fundamental building blocks benefit from the availability of high-Q resonators in the RF front-end, the analog baseband and the frequency synthesizer to lower power consumption, phase noise and die area. In addition, the compatibility of MEMS with CMOS opens the door to a higher integration level using for example an above-IC approach. This paper presents the recent work made at CSEM in the field of ultra low-power transceiver for wireless sensor network applications. It first presents the high-Q resonators, including the BAW resonators used in the RF front-end and in the RF oscillator together with MEMS used in the low frequency oscillators and IF section. These MEMS are activated thanks to an A1N piezo layer avoiding the need for high voltage generation which is incompatible with the low-power and low-voltage requirement. These MEMS are also temperature compensated by the combination of additional layers and electronics means. The paper then focuses on the main building blocks that can take advantage of high-Q resonators starting with the RF front-end. The fundamentals of oscillators built around high-Q devices is described, highlighting the basic trade-offs. Finally, new approaches for the analog baseband are described. This includes an example of a quadrature Sigma-Delta converter combining the different functions of anti-alias and image-reject filter together with analog-to-digital conversion. An alternative to traditional Sigma-Delta oversampled converters is the use of phase analog-to-digital converters to directly quantize the phase information without the need to convert the amplitude. This innovative approach can save power and complexity for all wireless applications using phase or frequency modulations.

Digital receiver architectures for the IEEE 802.15.4 standard

This paper describes an analysis of different digital radio receiver architectures for the IEEE 802.15.4 standard, focusing on the analog-to-digital converter (ADC). This standard has been developed for low bit-rate, low-power wireless personal area networks (WPAN). The choice of the best architecture depends on many factors, among which the power consumption, the integration suitability, the image rejection, the flicker and quantization noise, etc. There are mainly three basic architectures suitable for a low-power implementation: a) the direct conversion, b) the low-IF with low-pass /spl Delta//spl Sigma/ ADC and c) the low-IF with quadrature bandpass /spl Delta//spl Sigma/ ADC. Each of these architecture is analyzed in order to identify the trade-offs and select the most suitable for the IEEE 802.15.4 standard.

A low power miniaturized 1.95mm 2 fully integrated transceiver with fastPLL mode for IEEE 802.15.4/bluetooth smart and proprietary 2.4GHz applications

This paper presents an ultra-low power miniaturized single chip transceiver operating in the ISM band at 2.4GHz. Targeting low power and minimum die size, while excluding RF-options and minimizing the count of external components for low-cost, asks for appropriate architectural choices to obtain high performance. Fast PLL locking and immediate RX-TX turn-around minimize the consumption overhead at wake-up and turn-around. With a die size of only 1.95mm2 in a 90nm standard digital CMOS technology, the receiver achieves a sensitivity of -94.5dBm (1Mbps, BER 10E-3) while consuming only 7.1mA and the transmitter consumes 9.2mA for 0dBm output power. The base-band is compliant with the IEEE 802.15.4 standard, the Bluetooth Smart standard (former Bluetooth low energy BLE) and can be configured for proprietary standards at 2.4GHz, with data-rates up to 3Mbps.

A 1V 450μ W Quadrature Bandpass ΔΣ Modulator for the IEEE 802.15.4 Standard

This paper describes the design and implementation of a 2nd-order continuous-time quadrature bandpass ΔΣ modulator for wireless sensor networks (WSN) using the IEEE 802.15.4 standard. The design is focused on the constraints of low power consumption, low supply voltage and low complexity imposed by WSN. The availability of I and Q signals in the low-IF receiver enables a quadrature architecture which allows combining signal filtering, image rejection and quantization noise reduction. A continuous-time Gm-C implementation further combines the anti-alias function within the ADC and allows achieving the 1V operation. The quadrature ΔΣ modulator is integrated in a 0.18μm standard digital process. It is clocked at 72MHz and the center frequency is set at 3.75MHz with a bandwidth of 3MHz. The maximum measured signal-to-noise ratio is 36dB and the power consumption is only 450μW under 1V.

A 51.4 Mb/s FSK transmitter employing a Phase Domain Digital Synthesizer with 1.5 µs start-up for energy efficient duty cycling

This paper presents a low start-up latency Transmitter (TX) that can achieve FSK data rates of upto 51.4 Mb/s for deployment in duty cycled microsensor nodes. Utilizing a Phase Domain Digital Synthesizer with an FBAR frequency reference, this TX has a start-up latency of just 1.5 μs. It has been integrated in a 65nm technology and outputs upto 3 dBm power. It achieves a phase noise of -110 dBc/Hz at 1 MHz offset and has a frequency coverage of 2.17 - 2.47 GHz. The power consumption of this TX (including the Digital Baseband) varies from 15 mW at 1.2 Mb/s to 21.4 mW at 51.4 Mb/s. At peak data rate, this leads to an Duty-Cycling-Energy/bit (which takes into account the start-up energy) of 500 pJ/b for transmitting packets of length 32 bytes. Moreover, the TX incorporates a Hybrid Requantizer circuit which helps to trade off in-band noise with the spurs due to the non-linearity induced ΣΔ noise folding.

A 32 kHz DTCXO RTC Module with an Overall Accuracy of ±1 ppm and an All-Digital 0.1 ppm Compensation-Resolution Scheme

This paper presents an ultralow power (240 nA), wide voltage range (1.25–5.5 V), temperature-compensated RTC module achieving a typical accuracy of ±1 ppm at 1 Hz over the industrial temperature range of −40 to 85 °C. This is obtained by combining a miniature tuning fork 32 kHz XTALs with an ASIC in a miniature 8-pin ceramic package measuring only 3.2×1.5×0.8 mm3. An innovative patented all-digital interpolation scheme allows the accurate generation of a one pulse per second (1 PPS) signal with a resolution of 0.1 ppm permitting significant savings in terms of both the circuit area and power consumption (4×) compared to previously available such products.

11.5 A 3.2×1.5×0.8mm3 240nA 1.25-to-5.5V 32kHz-DTCXO RTC module with an overall accuracy of µ1ppm and an all-digital 0.1ppm compensation-resolution scheme at 1Hz

Timekeeping based on a 32kHz XTAL still remains the most popular, cost effective, low power, accurate solution for low-power portable applications. Simple solutions with overall accuracies of a few 100ppm are based on the combination of a through-hole or SMD XTAL together with an oscillator implemented as part of the application SoC (micro-controller, cell phone). As a single-ppm error represents a deviation of 30s/year (nearly 1 hour/year at 100ppm!), temperature-compensated XTAL or MEMS oscillators (TCXO, TCMO) used for time-keeping applications have received significant research attention over the last decade, driven by further miniaturization, tighter accuracy and lower power consumption needs [1-4]. Combining both resonator and oscillator intimately or even better, in a single package, leads to superior stability, improved robustness and lower consumption by minimizing environmental effects (moisture, temperature gradients) and stray capacitance. Real-time clock (RTC) modules integrating further time, timer, calendar, time stamping and alarm functions have become a key power-management block capable of scheduling precise wake-up at user- or pre-defined intervals so that a more complex, energy-constrained application can be heavily duty-cycled and left mostly hibernating (e.g., wireless sensor node). They are found in a variety of consumer, metering, medical, wearable, automotive, communication, outdoor, safety, and automation applications, and are a key component of the upcoming IoE revolution.

A ΣΔ based direct all-digital frequency synthesizer with 20 Mbps frequency modulation capability and 3μs startup latency

This paper presents an all-digital, direct frequency synthesizer that can support direct modulation data rates up to 20 Mbps for deployment in multi-hop, reconfigurable wireless mesh networks. In addition, this synthesizer can start up in only 3 us which reduces the energy overhead, thus making it attractive for duty cycling. By digitally manipulating time-shifted copies of a temperature-compensated FBAR oscillator signal based on the outputs from a Sigma-Delta modulator (SDM), the synthesizer is able to generate the desired frequency over a wide range. Integrated in a 65 nm CMOS technology, a prototype of this synthesizer generates frequencies from 2.34-2.47 GHz. Being completely digital, this synthesizer occupies a very small area of just 0.035 mm2. The synthesizer consumes 3.9 mA from a 1.1 V supply while achieving a frequency resolution of 180 Hz.

A 700 pJ/bit, 2.4 GHz, narrowband, PLL-free burst mode transmitter based on an FBAR with 5μs startup time for highly duty-cycled systems

This paper presents a PLL-free transmitter based on an FBAR achieving a 5μs startup time to reduce the crystal oscillator power overhead which degrades the energy efficiency for heavily duty cycled systems. The TX upconverts a FSK-modulated FBAR DCO signal with the IF output of a Phase Switching Divider (PSD) injection locked to the DCO. The PSD has a division step of 0.2 to circumvent the limited FBAR tuning range that prevents addressing all the channels in the various bands between 2.36 and 2.5 GHz. Integrated in a 65nm technology, the TX outputs -1dBm and consumes 9.2mA at 1.2V. Further, the TX is capable of data rates up to 16 Mbps leading to a peak energy efficiency of 700pJ/b as well as a multi-fold reduction in the mean power dissipation at lower mean data rates.