Daniele D. Caviglia

An experimental analog VLSI neural network with on-chip back-propagation learning

Analog VLSI implementations of artificial neural networks are usually considered efficient for the small area and the low power consumption they require, but very poor in terms of programmability. In this paper, we present an approach to the design of analog VLSI neural information-processing systems with on-chip learning capabilities. We describe a set of analog circuits for implementing the neural computational primitives of a Multi-Layer Perceptron, including the ones supporting a gradient-based learning algorithm (Back Propagation). Only supervision tasks are managed off chip.An experimental chip has been designed and fabricated using a standard digital 1.5 μm CMOS N-well technology. The chip contains 4 neurons and 32 synapses organized into a single-layer architecture with 8 inputs and 4 outputs. Measures illustrating the chip behavior during learning are reported.

Effects of weight discretization on the back propagation learning method: algorithm design and hardware realization

An architectural configuration for the back-propagation (BP) algorithm is illustrated. The circuit solution for the basic blocks is presented, and the effect of weight discretization on the BP algorithm is analyzed. It is demonstrated, through simulations, how the BP algorithm can be operated successfully with discretized weights. In particular, better performances can be achieved with an exponential discretization, i.e. the strength of weights varies exponentially with the controlling variable (voltage). The discretized voltage values differ by a quantity high enough that the neural network can be backed up with a refresh technique in combination with a multilevel dynamic memory that entails a particularly low wiring cost. A quasi-analog adaptive architecture is devised, properly matching the BP algorithm, and its CMOS circuit implementation is detailed. The mechanism controlling weight changes is simple enough to be reproduced locally at each synapsis site, thus meeting one of the requirements for an efficient storage technology for analog VLSI

Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing

The voltage controlled oscillator (VCO) is a fundamental block in RF IC architectures. Todays wireless communication applications do require a high level of performances from such a circuit, and specifically its phase noise figure and its power consumption. In fact, modern standards often demand for phase noise level better than -95 dBc/Hz at 100 KHz in the vast majority of cases, with supply voltages approaching the 1 V range. This paper presents the design challenges of a cross-coupled 1.8 GHz CMOS voltage controlled oscillator with a tuning range of 7%, and a phase noise figure of -113 dBc/Hz at an offset frequency of 100 KHz. It employs a resistor for biasing, avoiding in this way the common tail current source based on active circuitry (e.g. current mirrors in CMOS designs). This choice prevents the 1/f device noise upconversion, leading to an improved spectral purity. Since phase noise also varies with the reciprocal of the tail current, a trade-off can be established between noise performances and power consumption by simply changing the biasing resistor. The same circuit topology may thus be useful for building VCOs whose applications range from high performance wireless standards where an extremely low phase noise is mandatory, to low-cost portable systems where the reduced power drain is of major concern

A Circuit Architecture for Analog On-Chip Back Propagation Learning with Local Learning Rate Adaptation

In this paper we present the analog CMOS architecture of a Multi Layer Perceptron network with on-chip stochastic Back Propagation learning. The learning algorithm is based on a local learning rate adaptation technique which makes the on-chip implementation more efficient (i.e. fast convergence speed) with respect to similar architectures presented in the literature. Circuit simulation results on the XOR learning problem validate the network behavior.

An analog VLSI implementation of a feature extractor for real time optical character recognition

The architecture, the design, and the analog very large scale integration (VLSI) implementation of a feature extractor chip for optical character recognition (OCR) systems are described. The chip extracts a set of 112 feature values coded by current signals from a 32/spl times/24 digital pixel matrix, representing the input character. Such features are applied to a classifier (for example, a neural classifier) performing the recognition task. The measurements performed on that chip confirm its functionality. The chip can be used with a segmented and nonsegmented string of characters. A throughput of about 140 kChar/s is achieved for the segmented case, while a throughput of about 450 kChar/s is achieved for the nonsegmented case. The OCR architecture has been functionally validated. A set of numerical handwritten characters has been processed by the chip and the measured output features (after a normalization operation) have been used as input for neural network classifier; implemented by a software simulator which performs the recognition task. The resulting classification error rate (4.3%) has been successfully compared with those obtained by a high level model of this chip, and the results validate the entire architecture.

Differential Cross-Coupled CMOS VCOs with Resistive and Inductive Tail Biasing

Todays Wireless Communication Systems need very high performance VCOs. In many cases, phase noise levels better than -100 dBc/Hz@100 kHz have to be reached with a power consumption lower than 10 mW. This work presents a 1.8 GHz CMOS VCO with a phase noise of -113 dBc/Hz@100 kHz, where a bias resistor avoids the MOS active current source and its related noise, while a tail inductor allows truly differential operation.

An on-chip learning neural network

We present and discuss the major results of our research activity aimed to the analog VLSI implementation of on-chip learning neural networks. In particular we present the SLANP (self learning neural processor) chip results. The SLANP architecture implements an on-chip learning multilayer perceptron network. The learning algorithm is based on the back propagation but it exhibits increased capabilities due to the local learning rate management. A prototype chip has been designed and fabricated in a CMOS 0.7 /spl mu/m minimum channel length technology. The experimental results confirm the functionality of the chip and the soundness of the approach. The SLANP performance compares favorably with that reported in the literature.

Evaluation of gradient descent learning algorithms with an adaptive local rate technique for hierarchical feedforward architectures

Gradient descent learning algorithms (namely backpropagation and weight perturbation) can significantly increase their classification performances by adopting a local and adaptive learning rate management approach. We present the results of the comparison of the classification performance of the two algorithms in a tough application: quality control analysis in the steel industry. The feedforward network is hierarchically organized (i.e. tree of multilayer perceptrons). The comparison has been performed starting from the same operating conditions (i.e. network topology, stopping criterion, etc.): the results show that the probability of correct classification is significantly better for the weight perturbation algorithm.

An analog on-chip learning circuit architecture of the weight perturbation algorithm

In this paper we present the analog on-chip learning architecture of a gradient descent learning algorithm: the Weight Perturbation learning algorithm. From the circuit implementation point of view our approach is based on current mode and translinear operated circuits. The proposed architecture is very efficient in terms of speed, size, precision and power consumption; moreover it exhibits also high scalability and modularity.

Analog CMOS current mode neural primitives

The CMOS circuit implementation of the feedforward neural primitives of a generic Multi Layer Perceptron network is presented. Basically our approach is based on current mode computation and is aimed at a low power/low voltage circuit implementation; moreover, it is easily scalable to implement networks of any size. Experimental results are reported.