Gian Marco Bo

Analog VLSI circuits as physical structures for perception in early visual tasks

A variety of computational tasks in early vision can be formulated through lattice networks. The cooperative action of these networks depends on the topology of interconnections, both feedforward and recurrent ones. This paper shows that it is possible to consider a distinct general architectural solution for all recurrent computations of any given order. The Gabor-like impulse response of a second-order network is analyzed in detail, pointing out how a near-optimal filtering behavior in space and frequency domains can be achieved through excitatory/inhibitory interactions without impairing the stability of the system. These architectures can be mapped, very efficiently at transistor level, on very large scale integration (VLSI) structures operating as analog perceptual engines. The problem of hardware implementation of early vision tasks can, indeed, be tackled by combining these perceptual agents through suitable weighted sums. A 17-node analog current-mode VLSI circuit has been implemented on a CMOS 2 microm, NWELL, single-poly, and double-metal technology, to demonstrate the feasibility of the approach. Applications of the perceptual engine to various machine vision algorithms are proposed.

A Circuit Architecture for Analog On-Chip Back Propagation Learning with Local Learning Rate Adaptation

In this paper we present the analog CMOS architecture of a Multi Layer Perceptron network with on-chip stochastic Back Propagation learning. The learning algorithm is based on a local learning rate adaptation technique which makes the on-chip implementation more efficient (i.e. fast convergence speed) with respect to similar architectures presented in the literature. Circuit simulation results on the XOR learning problem validate the network behavior.

An analog VLSI implementation of a feature extractor for real time optical character recognition

The architecture, the design, and the analog very large scale integration (VLSI) implementation of a feature extractor chip for optical character recognition (OCR) systems are described. The chip extracts a set of 112 feature values coded by current signals from a 32/spl times/24 digital pixel matrix, representing the input character. Such features are applied to a classifier (for example, a neural classifier) performing the recognition task. The measurements performed on that chip confirm its functionality. The chip can be used with a segmented and nonsegmented string of characters. A throughput of about 140 kChar/s is achieved for the segmented case, while a throughput of about 450 kChar/s is achieved for the nonsegmented case. The OCR architecture has been functionally validated. A set of numerical handwritten characters has been processed by the chip and the measured output features (after a normalization operation) have been used as input for neural network classifier; implemented by a software simulator which performs the recognition task. The resulting classification error rate (4.3%) has been successfully compared with those obtained by a high level model of this chip, and the results validate the entire architecture.

An on-chip learning neural network

We present and discuss the major results of our research activity aimed to the analog VLSI implementation of on-chip learning neural networks. In particular we present the SLANP (self learning neural processor) chip results. The SLANP architecture implements an on-chip learning multilayer perceptron network. The learning algorithm is based on the back propagation but it exhibits increased capabilities due to the local learning rate management. A prototype chip has been designed and fabricated in a CMOS 0.7 /spl mu/m minimum channel length technology. The experimental results confirm the functionality of the chip and the soundness of the approach. The SLANP performance compares favorably with that reported in the literature.

An analog on-chip learning circuit architecture of the weight perturbation algorithm

In this paper we present the analog on-chip learning architecture of a gradient descent learning algorithm: the Weight Perturbation learning algorithm. From the circuit implementation point of view our approach is based on current mode and translinear operated circuits. The proposed architecture is very efficient in terms of speed, size, precision and power consumption; moreover it exhibits also high scalability and modularity.

Analog CMOS current mode neural primitives

The CMOS circuit implementation of the feedforward neural primitives of a generic Multi Layer Perceptron network is presented. Basically our approach is based on current mode computation and is aimed at a low power/low voltage circuit implementation; moreover, it is easily scalable to implement networks of any size. Experimental results are reported.

A Hardware Implementation of Hierarchical Neural Networks for Real-Time Quality Contol Systems in Industrial Applications

In this paper a real-time quality control system for steel industry is presented. The system implements the surface defect classification of steel strips in flat rolled mills in real-time. To achieve reliable classification accuracy the system implements a MLP_based hierarchical neural network. A dedicated hardware implementation has been designed and manufactured to meet the realtime constraints of the application. An ASIC neural chip directly implements the neural network and it is integrated on a custom high speed co-processor board, compatible with many commercial carrier board. The entire system has been tested with data coming from the plant.

An Analog VLSI Computational Engine for Early Vision Tasks

The computational capabilities of linear lattice network has been investigated through the analysis, synthesys and realization of CMOS circuits able to implement the 1-D convolution with Gabor-like operators. The area of the single processing cell is 83μm × 70 μm. The feasibility of the approach has been verified experimentally over a network of various sizes, up to 36 cells. Applications to stereopsys and motion analysis are described.

A VLSI architecture for weight perturbation on chip learning implementation

In this paper we present the analog on-chip learning architecture of a gradient descent learning algorithm: the weight perturbation learning algorithm. From the circuit implementation point of view our approach is based on current mode and translinear operated circuits. The proposed architecture is very efficient in terms of speed, size, precision and power consumption; moreover it exhibits also high scalability and modularity.

A Reconfigurable Analog VLSI Neural Network Architecture with Non Linear Synapses

A reconfigurable analog VLSI neural network architecture is presented: it is composed of non linear synapses and linear neurons and it implements a Multi Layer Perceptron network which can be trained by using the standard Back Propagation algorithm. The reconfigurability allows to change the interconnections between synapses, thus programming the topology of the network without any modification of the off-chip wiring. The architecture features a greater robustness with respect to noise and to errors introduced during the computations if compared to others presented in the literature.