Danielle Griffith

A 120nW 18.5kHz RC oscillator with comparator offset cancellation for ±0.25% temperature stability

Integrated low-frequency oscillators can replace crystal oscillators as sleep-mode timers to reduce the size and cost of wireless sensors [1]. Since the timer is one of the few continuously functioning circuits, minimizing its power consumption can greatly reduce sleep-mode power of highly duty-cycled systems. Temperature stability of the oscillator is important in order to minimize timing uncertainly and guard time for the radios, and thus maximizing sleep time. The voltage-averaging feedback method described in [2] achieves high stability in the MHz frequencies, but when scaled to the kHz range, requires very large filters. On the other extreme, gate leakage-based timers have been designed for sub-nW power consumption, but operate in the sub-Hz frequencies [3]. In the past, high accuracy RC oscillators in the kHz range have been designed with feed-forward correction [1] and self-chopped operation [4]. In this work, an offset cancellation architecture achieves long-term frequency stability and temperature stability while operating at lower power.

A WCDMA, GSM/GPRS/EDGE receiver front end without interstage SAW filter

A dual mode RF receiver for DCS band in 90 nm CMOS is presented. The receiver uses direct conversion for WCDMA mode and uses 100 kHz low IF for GSM/GPRS/EDGE (GGE) mode. The receiver does not use an interstage SAW filter between LNA and mixer. The mixer stage is followed by a variable gain amplifier. Two times LO clock is provided from external source and a divide by two is used to generate quadrature clocks. The receiver has a NF of 2.9 dB and meets all the out of band and in band linearity requirements for both WCDMA and GGE modes

17.8 A 190nW 33kHz RC oscillator with ±0.21% temperature stability and 4ppm long-term stability

In wireless networks with a low duty cycle, the radio is operational for only a small percentage of the time. A sleep timer is used to synchronize the data transmission and reception. The total system power is then limited by the sleep power and the sleep timer frequency stability. Low-frequency crystal oscillators are a common choice for sleep timers due to their excellent long-term stability, frequency stability over temperature, and very low power consumption. However, the external crystal cost and board area are undesired. If an integrated oscillator is used as an alternative, the frequency variation must be minimized so the sleep time can be maximized.

A 65nm CMOS DCXO system for generating 38.4MHz and a real time clock from a single crystal in 0.09mm 2

An integrated digitally-controlled crystal oscillator (DCXO) is presented that generates both 38.4 MHz and also a 32.768 kHz real time clock (RTC) from a single 38.4 MHz crystal. The DCXO can startup independently and transition seamlessly in and out of software control. The tuning range is 280 ppm with 2 ppb/step and guaranteed monotonicity. The phase noise is -135 dBc/Hz at 1kHz offset and -146 dBc/Hz at 10 kHz offset. The current consumption is 5 mA from a 1.4 V supply in full power mode and 234 μA in low power mode, including the LDO and all clock buffers. The DCXO is implemented in standard 65 nm digital CMOS with a die area of 0.09mm2.

5.9 A 24MHz crystal oscillator with robust fast start-up using dithered injection

Wireless nodes in Internet-of-Everything (IoE) applications achieve low power consumption by operating the radio at very low duty cycles. The wireless node spends most of its time in sleep, waking only occasionally to transmit or receive data. For some standards, such as Bluetooth Low Energy (BLE), the data or advertising packet length can be less than the time it takes the crystal oscillator, which is used as the reference clock for the radios PLL, to turn on. Figure 5.9.1 shows a simplified power profile for a node with a typical BLE advertising packet length. A significant fraction of energy used for each RX/TX burst is used to turn on the oscillator. For applications where average power is not dominated by sleep power, the crystal oscillator start-up time can be a large contributor to average power consumption.

An RC Oscillator With Comparator Offset Cancellation

A fully-integrated 18.5 kHz RC time-constant-based oscillator is designed in 65 nm CMOS for sleep-mode timers in wireless sensors. A comparator offset cancellation scheme achieves 4× to 25× temperature stability improvement, leading to an accuracy of ±0.18% to ±0.55% over -40 to 90 °C. Sub-threshold operation and low-swing oscillations result in ultra-low power consumption of 130 nW. The architecture also provides timing noise suppression, leading to 10× reduction in long-term Allan deviation. It is measured to have a stability of 20 ppm or better for measurement intervals over 0.5 s. The oscillator also has a fast startup-time, with the period settling in 4 cycles.

RF receiver front-end with +3dBm out-of-band IIP3 and 3.4dB NF in 45nm CMOS for 3G and beyond

A receiver front-end in standard 45 nm CMOS technology is presented. The receiver achieves WCDMA system performance without requirement for an inter-stage SAW filter. High out-of-band linearity performance is achieved by reducing the RF circuitry and filtering the out-of-band blockers after direct conversion. For the receiver at 1.9 GHz, a +3.1 dBm IIP3 is achieved for blockers at 40 MHz and 80 MHz away from the RF carrier. NF is 3.4 dB, out-of-band IIP2 is +51 dBm and current is 19.5 mA for both I, Q channels with VDD of 1.4 V. LO is provided using an on-chip VCO followed by a quadrature divider.

A 1.9nJ/bit, 5Mbps multi-standard ISM band wireless transmitter using fully digital PLL

This paper presents an energy efficient transmitter for multi-standard applications (IEEE802.15.4, BLE, 5Mbps) in ISM2.4GHz band. It incorporates a fully digital PLL with two point modulation to achieve upto 5Mbps data rate at 9.5mW power consumption (including all power management blocks) at 0dBm output power, leading to 1.9nJ/b efficiency. The proposed digital PLL uses a counter based area and power efficient re-circulating TDC, current reuse low area DCO using resistive tail, process compensated high speed divider, class-AB PA stages, and fully integrated on-chip LDOs. The entire transmitter occupies 0.35mm2 Silicon area in a 65nm digital CMOS process.

A +7.9dBm IIP3 LNA for CDMA2000 in a 90nm digital CMOS process

A highly linear low noise amplifier (LNA) has been implemented in a standard digital 90nm CMOS process. At 880MHz the amplifier provides a forward power gain (S21) of 14.5dB with a supply voltage of 1.4V and a current consumption of 8.3mA. The noise figure was measured to be 1.0dB and the input third order intercept point (IP3) is +7.9dBm. Two lower gain modes have also been implemented; one with a lower transconductance gain stage, and one with a bypass switch. These performance parameters make the amplifier suited for the CDMA2000 cellular standard

5.9 A 37μW dual-mode crystal oscillator for single-crystal radios

A dual mode crystal oscillator has been implemented that can be used both as the reference clock for the radio PLL in a high performance mode the sleep timer in a low power mode. The oscillator can switch seamlessly between the high performance and low power modes without losing the time base so that synchronization can be maintained among wireless nodes. This the wireless node to be implemented with a single crystal, enabling a low and small form factor design.