Per Torstein Roine

17.8 A 190nW 33kHz RC oscillator with ±0.21% temperature stability and 4ppm long-term stability

In wireless networks with a low duty cycle, the radio is operational for only a small percentage of the time. A sleep timer is used to synchronize the data transmission and reception. The total system power is then limited by the sleep power and the sleep timer frequency stability. Low-frequency crystal oscillators are a common choice for sleep timers due to their excellent long-term stability, frequency stability over temperature, and very low power consumption. However, the external crystal cost and board area are undesired. If an integrated oscillator is used as an alternative, the frequency variation must be minimized so the sleep time can be maximized.

5.9 A 24MHz crystal oscillator with robust fast start-up using dithered injection

Wireless nodes in Internet-of-Everything (IoE) applications achieve low power consumption by operating the radio at very low duty cycles. The wireless node spends most of its time in sleep, waking only occasionally to transmit or receive data. For some standards, such as Bluetooth Low Energy (BLE), the data or advertising packet length can be less than the time it takes the crystal oscillator, which is used as the reference clock for the radios PLL, to turn on. Figure 5.9.1 shows a simplified power profile for a node with a typical BLE advertising packet length. A significant fraction of energy used for each RX/TX burst is used to turn on the oscillator. For applications where average power is not dominated by sleep power, the crystal oscillator start-up time can be a large contributor to average power consumption.

Process compensated low power LO divider chain with asynchronous odd integer 50% duty cycle CML dividers

This paper illustrates the design of a process compensated bias for asynchronous CML dividers for a low power, high performance LO divide chain operating at 4Ghz of input RF frequency. The divider chain provides division by 4,8,12,16,20, and 24. It provides a differential CML level signal for the in-loop modulated transmitter, and 25% duty cycle non-overlapping rail to rail waveforms for I/Q receiver for driving passive mixer. Asynchronous dividers have been used to realize divide by 3 and 5 with 50% duty cycle, quadrature outputs. All the CML dividers use a process compensated bias to compensate for load resistor variation and tail current variation using dual analog feedback loops. Frabricated in 180nm CMOS technology, the divider chain operate over industrial temperature range (−40 to 90°C), and provide outputs in 138–960Mhz range, consuming 2.2mA from 1.8V regulated supply at the highest output frequency.

5.9 A 37μW dual-mode crystal oscillator for single-crystal radios

A dual mode crystal oscillator has been implemented that can be used both as the reference clock for the radio PLL in a high performance mode the sleep timer in a low power mode. The oscillator can switch seamlessly between the high performance and low power modes without losing the time base so that synchronization can be maintained among wireless nodes. This the wireless node to be implemented with a single crystal, enabling a low and small form factor design.

A ±10ppm −40 to 125°C BAW-based frequency reference system for crystal-less wireless sensor nodes

A frequency reference system is implemented with a BAW-based 2.52GHz oscillator, divider, temperature sensor, digital PLL, and final test at three temperatures to create a 48MHz reference frequency with +/−10ppm stability from −40 to 125°C. This reference clock periodically recalibrates a fully integrated 32kHz RC oscillator to less than +/−500ppm frequency variation so that it can be used as the wireless node sleep timer. The reference system enables a Bluetooth Low Energy compliant radio in 65nm CMOS to be realized without any crystals.

A crystal-less bluetooth low energy radio using a MEMS-based frequency reference system

A system clock is implemented with a 2.52 GHz MEMS-based oscillator, divider, temperature sensor, digital PLL, and active temperature compensation to generate a 48 MHz frequency reference with ±10 ppm stability from −40°C to 105°C. An on-chip 32 kHz RC oscillator is also periodically calibrated by this reference clock to achieve ±500 ppm accuracy, allowing it to be used as the wireless node sleep timer. Additionally, the MEMS oscillator is advantaged in highly duty cycled protocols due to its 100x faster start-up time. This fully integrated reference system enables a crystal-less Bluetooth Low Energy compliant radio in 65 nm CMOS and could provide on-board design convenience to end users.

A low power low phase noise fractional-N synthesizer with linearization and mismatch noise shaping techniques for sub-GHz multi-band transceiver with narrow channel spacing

A fractional-N frequency synthesizer with a linearized phase-frequency detector and noise shaping of phase mismatch is presented. These techniques lead to spurious free operation over a wide frequency range (133-960M), and 15dB close in phase noise improvement. The core PLL consumes 15mW in 180nm CMOS and provides phase noise better than -94dBc/Hz@1kHz from a 924MHz carrier.