Danny Luu

10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver

The authors report the implementation of a continuous-time linear equalizer (CTLE) featuring a new technique to control the high-frequency gain peaking and to interface to current-summing stages usually implemented as interleaved slices for the linear analog superposition of the coefficients of decision-feedback equalizers (DFE). The circuits are implemented in 14nm FinFET SOI CMOS technology and are included in a prototype receiver targeted to 16Gb/s serial I/O links for multi-core microprocessors off-chip communication. The architecture is shown in the paper. Power efficiency and compactness are among the primary goals of the study together with an equalization capability sufficient to recover at bit-error rate (BER) levels below 10-12 data transmitted across smooth channels with losses in excess of 25dB at 8GHz.

A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS

This paper describes the implementation of a 4-level pulse-amplitude-modulation (4-PAM) receiver consisting of a 6-bit time-interleaved successive-approximation analog-to-digital converter (TI-SAR ADC), followed by a fully digital speculative 2-tap decision-feedback equalizer (DFE) operating at one-fourth of the modulation rate. The receiver, implemented in an experimental chip fabricated in 32 nm SOI CMOS, is designed to recover data at 56Gb/s over a channel with an attenuation of 11 dB at 14 GHz. The power consumption of the receiver is 202.7 mW at a supply of 1.2 V, achieving an overall energy efficiency of 3.62 pJ/b. The DFE along with area-optimized register arrays and memory-control buffers occupies an area of 0.154×0.169 mm2. Experimental results demonstrating a BER<;10-8 are obtained using a (27-1)-bit pseudo-random binary sequence (PRBS-7).

28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET

High-speed SAR ADCs became popular with modern CMOS technologies because of their mostly digital logic, making them highly suitable for compact and power-efficient multi-GS/s time-interleaved ADCs. As many applications cannot tolerate input swings ≥1Vppd, comparator noise limits the SNDR of SAR ADCs, making gain stages necessary for higher SNDR - either as comparator pre-amplifiers or between pipelined stages. Pre-amplifiers significantly reduce the conversion speed of the ADC, but they provide maximum SNDR because linearity of the amplifier is irrelevant. An interstage amplifier for pipelining best suits mid-resolution SAR ADCs, where the required linearity is limited. Moreover, pipelining results in higher conversion speeds and power efficiency because the gain stage is used only once per conversion [1]. This work presents a pipelined-SAR ADC architecture that exceeds the conversion speed of previous pipelined and single-stage SAR ADCs. The ADC achieves 50dB SNDR and 950MS/s at 2.26mW, and 1.5GS/s at 6.92mW on an area of 0.0016mm2.

23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path

The demand for energy-efficient I/O link transceivers operating at raw data-rates in the tens of Gb/s continues to fuel innovation in the field of wireline communication [1]. Receiving equalizers under one pJ/b are sought for chip-to-chip and chip-to-module links designed to operate across short-reach copper channels. Standards such as CEI-28G-VSR suit chip-to-module communication at raw data rates up to 28Gb/s and 10-12dB insertion loss at Nyquist. Proprietary and open standards in the same speed range are being developed too for data and memory-centric systems co-designed with CPUs and GPUs and channels with insertion loss on the order of 20dB [2].

A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET

A 300MS/s 12b SAR ADC achieving 61.6dB peak SNDR is presented. It reaches 60.5dB SNDR and 78.7dB SFDR with 0.8Vpp,diff input amplitude at Nyquist. The key elements are a comparator with inverter-based preamplifier and a SAR-based common-mode regulation. The regulation adjusts the common mode on a sample-by-sample basis to improve common-mode rejection. The ADC consumes 7.0mW from a single 0.85V supply, where 3.7mW is contributed by the reference buffer.

29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET

The rapid increase of bandwidth requirements between processors in high-end servers motivates the integration of optical interconnects on the first-level processor package [1]. In this perspective, additional bandwidth density can be achieved by integrating optical transceivers directly into the processor die. Optically enabled CPUs can provide energy-efficient, low-latency interconnects over long distances (>10m) in future data-centers. Integrated photonic interconnect technology will require sensitive and low-power receiver (RX) circuits that operate at high data rates.

A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS

The implementation of a digital four-level pulse-amplitude-modulation reduced-state sliding-block Viterbi detector (VD) with two substates and two embedded per-survivor decision-feedback taps operating at one-eighth of the modulation rate is described. Implemented in an experimental chip fabricated in 14nm CMOS, the VD is designed to recover data at 25.6 Gb/s over an emulated time-dispersive channel. The power consumption of the VD together with the test circuitry is 105mW at a supply of 0.7V, achieving an overall energy efficiency of 4.1 pJ/b. At a supply of 0.8V, a data rate of 30.4 Gb/s is achieved with an energy efficiency of 5.3 pJ/b. The VD occupies an area of 0.507×0.717mm2. Experimental results showing system performance are obtained using a (215-1)-bit pseudo-random binary sequence. The impact on the bit error rate of the synchronization length for block initialization is also measured.

Design considerations for 50G+ backplane links

The constantly increasing need for I/O bandwidth push electrical backplane links to data rates of 50Gb/s and above. Although board materials have improved significantly, backplane links are increasingly limited by signal attenuation while suffering from ISI, jitter, device noise and cross-talk. In this paper we summarize these limitations, and show possible directions to cope with them in order to further extend the achievable data rate.

CMOS ADCs Towards 100 GS/s and Beyond

The implementation of a 64x time-interleaved ADC in 32nm CMOS SOI is analyzed. Measurement results confirm 33 dB SNDR up to 19.9 GHz at 90 GS/s and 1.2V supply. Architecture details and analysis show insights into limitations and potentials of the chosen architecture. In par-ticular the input bandwidth is of concern for ADCs at more than 64 GS/s, as a larger number of sampling switches in-creases the parasitic load and reduces the input bandwidth. Insights on a simplified analysis of interleaver structures and existing solutions to bandwidth issues are highlighted and show a path to extend the sampling speed of CMOS ADCs beyond 100 GS/s.

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cancelled out by decision-feedback equalizer (DFE). However, due to the existence of feedback loop in DFE, there is no trivial way to parallelize it, making it difficult to be realized in digital circuits for wireline RX based on analog-to-digital converter (ADC) with ≥ 56 Gb/s data rate. In this work, convolution theorem is applied for achieving parallel digital equalizer implementation. The digital equalizer datapath consists of discrete Fourier transform (DFT) core, inverse-DFT (IDFT) core, complex multipliers between DFT and IDFT cores, and overlap-add circuit. Design considerations for low-area VLSI implementation of such architecture is discussed.