Lukas Kull

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

Next-generation digital high-speed links require fast, yet energy-efficient ADCs at minimum area. Recent years saw impressive progress in SAR ADC designs towards higher sampling speed. Asynchronous clocking, redundant capacitive DACs (CDAC), multi-bit decisions per step and interleaved designs have been presented. We present an asynchronous redundant single-channel ADC achieving 1.2GS/s at 1V supply by using two comparators in alternation to relax comparator reset timing. The ADC achieves 39.3dB SNDR and 34fJ/conversion-step with a core chip area of 0.0015mm2.

4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm 2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS

For an on-chip or fully integrated microprocessor power-delivery system, the on-chip power converter must 1) be designed using the same technology as the microprocessor, 2) deliver high power density to supply a microprocessor core with small area overhead, 3) achieve high efficiency, and 4) perform fast regulation over a wide voltage range for dynamic voltage and frequency scaling (DVFS). On-chip switched-capacitor (SC) converters have gained increasing popularity for this application due to their ease of integration using only transistors and capacitors readily available in the chosen technologies [1-6].

A 4.6W/mm 2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS

The future trends in microprocessor supply current requirements represent a bottleneck for next generation high-performance microprocessors since the number of supply pins will constitute an increasingly larger fraction of the total number of package pins available. This leaves few pins available for signaling. On-chip power conversion is a means to overcome this limitation by increasing the input voltage - thereby reducing the input current - and performing the final power conversion on the chip itself. This paper details the design and implementation of on-chip switched capacitor converters in deep submicron technologies. High capacitance density deep trench capacitors with a low parasitic bottom plate capacitor ratio available in the technology facilitate high power density and efficiency in on-chip switched capacitor converter implementations. The measured performance of a 2 : 1 voltage conversion ratio on-chip switched capacitor converter implemented in 32nm SOI CMOS technology with 1.8V input voltage results in a power density of 4.6W/mm2 at 86% efficiency when operated at a switching frequency of 100MHz.

22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS

Forthcoming optical communication standards such as ITU OTU-4 and 100/400Gb/s Ethernet require ADCs with more than 50GS/s and at least 5 ENOB to enable complex equalization in the digital domain. SAR ADCs and interleaved ADCs made impressive progress in recent years. First CMOS ADCs with at least 6b and conversion rates exceeding 20GS/s were presented, proving that interleaved SAR ADCs are an optimal choice for high-speed ADCs with moderate resolution. We present an interleaved CMOS ADC architecture based on an asynchronous redundant SAR ADC core element. It was measured up to a sampling rate of 100GS/s and can be operated from a single supply voltage. At 90GS/s, the measured SNDR stays above 36.0dB SNDR up to 6.1GHz and 33.0dB up to 19.9GHz input frequency while consuming 667mW. The ADC is implemented in 32nm digital SOI CMOS and occupies 0.45mm2.

A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson–Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS

Tomlinson-Harashima (TH) precoding is a transmitter equalization technique in which the post-cursor intersymbol interference (ISI) is canceled by means of an infinite impulse response (IIR) filter with modulo (MOD)-based amplitude limitation. TH equalizers are suited for asymmetric links, such as DRAM interfaces, where the transmitter contains the equalization complexity and the receiver is kept simple. To increase the data rate, we propose the application of pipelining and half-rate operation to the ISI subtraction in the equalizers feedback path. A TH equalizer with 8 taps, 6 bit resolution, and 2-PAM/4-PAM support has been implemented in 22-nm silicon-on-insulator (SOI) CMOS technology. In measurements, the feedback delay reduction techniques allow us to equalize 34-cm-long PCB traces having 12-dB loss with 7 × ISI reduction for 5.0-Gb/s 2-PAM signaling, and in 10.0-Gb/s 4-PAM mode completely closed eye diagrams are opened. The measured efficiency of the 145 μm× 115 μm transmitter is 1.2 pJ/bit in 4-PAM mode at 5.0 Gbaud with disabled equalization and increases linearly with 14 μW/Gbaud per 1% increase of the equalization tap weights.

Temporal correlation detection using computational phase-change memory

Conventional computers based on the von Neumann architecture perform computation by repeatedly transferring data between their physically separated processing and memory units. As computation becomes increasingly data centric and the scalability limits in terms of performance and power are being reached, alternative computing paradigms with collocated computation and storage are actively being sought. A fascinating such approach is that of computational memory where the physics of nanoscale memory devices are used to perform certain computational tasks within the memory unit in a non-von Neumann manner. We present an experimental demonstration using one million phase change memory devices organized to perform a high-level computational primitive by exploiting the crystallization dynamics. Its result is imprinted in the conductance states of the memory devices. The results of using such a computational memory for processing real-world data sets show that this co-existence of computation and storage at the nanometer scale could enable ultra-dense, low-power, and massively-parallel computing systems.New computing paradigms, such as in-memory computing, are expected to overcome the limitations of conventional computing approaches. Sebastian et al. report a large-scale demonstration of computational phase change memory (PCM) by performing high-level computational primitives using one million PCM devices.

Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) for 100 Gb/s communication systems. The model is suitable for ADCs where the analog input bandwidth is of concern and enables a tradeoff between different architectures with respect to the analog input bandwidth, the hold time of the sampled signal, and constraints on the clock path. The two ADCs at 6 and 8 b resolution implement inline demux sampling with 32χ and 64χ interleaving to achieve 36 GS/s at 110 mW and 90 GS/s at 667 mW, respectively. The analog input bandwidth of both ADCs exceeds 20 GHz. The SNDR of the 64χ interleaved ADC is above 36 dB up to 6.1 GHz and above 33 dB up to 19.9 GHz at 90 GS/s, and the SNDR of the 32χ interleaved ADC exceeds 31.6 dB up to Nyquist at 36 GS/s. The 32χ and 64χ interleaved ADCs are optimized for area and occupy 0.048 and 0.45 mm2, respectively, in 32 nm CMOS SOI technology.

Room-temperature THz imaging based on antenna-coupled MOSFET bolometer

We report on the design, fabrication and measurements of a new THz sensor concept based on an antenna-coupled MOSFET bolometer for room-temperature passive THz imaging for security and medical-diagnostic applications. The device is fabricated in a 180-nm CMOS SOI technology followed by a post-CMOS MEMS process. In this sensor, the antenna absorbing the THz electromagnetic field is directly coupled to the bolometer for maximum energy collection, whereas its design aims at minimizing its thermal mass as is necessary for fast frame rates. DC measurements before and after the MEMS process as well as thermal time constant and THz antenna measurements are presented.

A 10 W On-Chip Switched Capacitor Voltage Regulator With Feedforward Regulation Capability for Granular Microprocessor Power Delivery

Granular power delivery with per-core regulation for microprocessor power delivery has the potential to significantly improve the energy efficiency of future data centers. On-chip switched capacitor converters can enable such granular power delivery with per-core regulation given a high efficiency, high power density, fast response time, and high output power converter design. This paper details the implementation of an on-chip switched capacitor voltage regulator in a 32 nm SOI CMOS technology with deep trench capacitors. A novel feedforward control for reconfigurable switched capacitor converters is presented. The feedforward control reduces the output voltage droop following a transient load step. This leads to a reduced minimum microprocessor supply voltage, thereby reducing the overall power consumption of the microprocessor. The implemented on-chip switched capacitor voltage regulator provides a 0.7-1.1 V output voltage from 1.8 V input. It achieves a 85.1% maximum efficiency at 3.2 W/mm2 power density, a subnanosecond response time with improved minimum supply voltage capability, and a maximum output power of 10 W. For an output voltage of 850 mV, the feedforward control reduces the required voltage overhead by 60 mV for a transient load step from 10% to 100% of the nominal load. This can reduce the overall power consumption of the microprocessor by 7%.

Antenna-Coupled MOSFET Bolometers for Uncooled THz Sensing

In this paper, we present a comprehensive study on the operation of an antenna-coupled THz bolometer based on a micro-machined SOI-CMOS thermal sensor. The pixels are designed to operate at room temperature in vacuum. We focus on a new planar skirt antenna, which combines high sensitivity within a 0.6-1.2 THz band and 30 ° HPBW. We present an overview of the design considerations, as well as the characterization results which were obtained with both broadband and CW THz sources. The NEP of the pixel is of the order of 25 pW/Hz 1/2, with responsivity 100 mA/W at the optimal operating point. The peak responsivity to a broadband THz signal is 600 mA/W. The ease of integration with a read-out circuit and the low power dissipation make this type of pixel a good candidate for focal plane array architecture.