Dante Del Corso

Architecture of a Small Low-Cost Satellite

This paper presents the architecture of a small university satellite that we have developed. The main design criteria were low cost and fault tolerance, which have been achieved by using commercial off the shelf components and by replicating all critical functions, while monitoring the state of the system for failures. The focus of the paper is on overall organization, design partitioning and details of the actual hardware. We show that the development of a low-cost satellite is feasible with a very limited budget.

Multi-microprocessor systems for real-time applications

1. Multiprocessor System Architecture.- 1.1 Distributed Processing and Multiprocessors.- 1.1.1 Classification Criteria.- 1.1.2 Computer Networks.- 1.1.3 Multiple Processor Systems.- 1.1.4 Special Purpose Machines.- 1.1.5 Other Classifications of Distributed Systems.- 1.2 Multiprocessor Systems.- 1.2.1 Multiprocessor Structures.- 1.2.2 The Interconnection Network.- 1.2.3 Shared Bus.- 1.2.4 Multiport Memory.- 1.2.5 Crossbar Switches.- 1.2.6 Multistage Interconnection Networks.- 1.2.7 Applications of Multiple Processors.- 1.3 Description Techniques for Multiprocessors.- 1.3.1 Levels of Description.- 1.3.2 Selection of the Description Level.- 1.3.3 The PMS Notation.- 1.3.4 The MSBI Notation.- 1.4 Some Multiprocessor Systems.- 1.4.1 Selection Criteria.- 1.4.2 The Cm*.- 1.4.3 The C.mmp.- 1.4.4 The PLURIBUS.- 1.4.5 The ?* System.- 1.4.6 The iAPX432 System.- 1.4.7 The TOMP Multiprocessor System.- 1.5 References.- 2. Performance Analysis of Multiprocessor Systems.- 2.1 Performance Evaluation of Bus Oriented Multiprocessor Systems.- 2.1.1 Introduction.- 2.1.2 Modeling Assumptions.- 2.1.3 The System Workload.- 2.1.4 Architecture 1.- 2.1.5 Architecture 2.- 2.1.6 Architecture 3.- 2.1.7 Architecture 4.- 2.1.8 Architecture Comparison.- 2.1.9 Choice of the Architecure of TOMP.- 2.2 Other Modeling Techniques and Measurements.- 2.2.1 Introduction.- 2.2.2 Stochastic Petri Net Models.- 2.2.3 Queueing Network Models.- 2.2.4 Measurements.- 2.3 References.- 3. TOMP Software.- 3.1 Introduction.- 3.1.1 Goals and Motivations.- 3.1.2 Limits.- 3.1.3 Overall System Description.- 3.2 Interprocess Communication.- 3.2.1 Model and Primitive Operations.- 3.2.2 Low Level Communication Protocol.- 3.3 The Executive.- 3.3.1 System Initialization.- 3.3.2 Process Management.- 3.3.3 Interrupt Handling.- 3.3.4 Monitoring Functions.- 3.4 Monitoring and Debug.- 3.4.1 General Architecture.- 3.4.2 Debugging Functions.- 3.5 Utilities.- 3.5.1 Terminal Handler.- 3.5.2 File System.- 3.5.3 Common Memory Allocator.- 3.6 System Generation.- 3.7 A Critical Review.- 3.8 References.- 4. Design of Multiprocessor Buses.- 4.1 Introduction.- 4.2 Basic Protocols.- 4.2.1 Elementary Operations.- 4.2.2 Types of Information Transfer Cycles.- 4.2.3 Synchronization of the Action Flow.- 4.3 Bused Systems.- 4.3.1 Channel Allocation Techniques.- 4.3.2 Bus Arbitration.- 4.3.3 The Distributed Self-selection Arbiter.- 4.4 Electrical Behaviour of Backplane Lines.- 4.4.1 Definition of Signal Levels.- 4.4.2 Transmission Line Effects.- 4.4.3 Crosstalk.- 4.4.4 Protocol Speed.- 4.5 Protocol Extension.- 4.5.1 The Enable/Disable Technique.- 4.5.2 Bus Supervisors.- 4.6 References.- 5. Some Examples of Multiprocessor Buses.- 5.1 Introduction.- 5.2 The Multibus Backplane.- 5.2.1 History and Main Features.- 5.2.2 Physical and Electrical Specifications.- 5.2.3 The Information Transfer Protocol.- 5.2.4 Special Features.- 5.2.5 Timing and Pinout.- 5.3 The VME Backplane Bus.- 5.3.1 History and Main Features.- 5.3.2 Physical and Electrical Specifications.- 5.3.3 The Information Transfer Protocol.- 5.3.4 Special Features.- 5.4 The 896 Backplane Bus.- 5.4.1 History and Main Features.- 5.4.2 Physical and Electrical Specifications.- 5.4.3 The Information Transfer Protocol.- 5.4.4 Special Features.- 5.4.5 Timing and Pinout.- 5.5 The M3BUS Backplane.- 5.5.1 History and Main Features.- 5.5.2 Physical and Electrical Specifications.- 5.5.3 System Organization and Control.- 5.5.4 The Arbitration Protocol.- 5.5.5 The Addressing Protocol.- 5.5.6 The Data Transfer Protocol.- 5.5.7 Interrupt and Interprocessor Communication.- 5.5.8 Supervisor Protocol.- 5.5.9 The Serial Bus.- 5.5.10 Timing and Pinout.- 5.6 References.- 6. Hardware Modules for Multiprocessor Systems.- 6.1 Introduction.- 6.2 System Design.- 6.2.1 Physical Organization of Multiprocessor Systems.- 6.2.2 Board Design Guidelines.- 6.3 Slave Modules.- 6.3.1 Organization of Slave Modules.- 6.3.2 Address Decoders and Latches.- 6.3.3 Slave Control Logic.- 6.3.4 Slave Buffering.- 6.4 Master Modules.- 6.4.1 Organization of Master Modules.- 6.4.2 External Access Decoder and Bus Arbitration.- 6.4.3 Master Control Logic.- 6.4.4 Master Buffering.- 6.5 Interrupt Structures.- 6.5.1 Requirements for Multiprocessor Systems.- 6.5.2 System Controls.- 6.5.3 Processor Interrupts.- 6.5.4 Centralized Interrupt Handler.- 6.5.5 Distributed Interrupt Handler.- 6.5.6 Serial Lines.- 6.6 Special Modules.- 6.6.1 Multiple-slave Modules.- 6.6.2 Bus Windows.- 6.6.3 Dual-port Slaves.- 6.6.4 Master-slave Modules.- 6.6.5 Block Transfer Units.- 6.6.6 Supervisor Modules.- 6.7 References.- 7. Multiprocessor Benchmarks.- 7.1 Introduction.- 7.2 The Concept of Performance.- 7.3 Parallel Programming.- 7.4 Parallel Notation Form.- 7.5 Parallel Sorting Techniques.- 7.6 Measurements and Analysis of Results.- 7.7 Conclusion.- 7.8 References.

Using Coherent Pulse Width and Edge Modulations in Artificial Neural Systems

This paper describes an existing silicon implementation of an artificial neural system based on coherent pulse width and edge modulation techniques. A chip set with different neural functions has been conceived, manufactured and tested. Neural circuits have been optimized for lowest computation energy and highest reconfigurability. The main device is a 32 x 32 synaptic array consuming 10 mW of power at 140 MCPS. Synapsis size is about 7.200 microns 2 using a standard 1.5 microns CMOS technology. The problem of interfacing robotic sensors and actuators is addressed: voltage, current and resistance-based sensors are considered for the measurement of physical quantities such as temperature, pressure, strain, etc. Low resolution imaging sensors for robotic vision are also considered.

Design of a University Nano-Satellite: the PiCPoT Case

Satellites are not necessarily something huge and expensive. Small satellites have been designed (or are being designed) by several universities. These satellites must fit within tight cost constraints, for the launch and the actual satellite hardware. Success in developing these satellites, and the related technologies and methods, would enable an easier access to space, especially for small and medium enterprises (SMEs), leading to new markets and applications. We present the architecture of a small university satellite that we developed. The main design criteria were low costs and fault tolerance. To meet the first one, we chose to use commercial off the shelf (COTS) components wherever possible. For the second one, we replicated all the satellite critical functions, using different technologies and solutions, while constantly monitoring the state of the system for failures. The focus is on overall organization, design partitioning, and details of the actual hardware. We show that the development of a low-cost satellite is feasible with a limited budget.

The 3DE custom course compiler: an engine to assemble custom web courses

The educational results of web courses can be improved through the development of modules customized for the requirements and needs of each learner. This task becomes feasible only if automated tools for course compilation are available; such tools are developed in the 3DE project. The core of the 3DE system is the Custom Course Compiler: it assembles micromodules in courses, taking into account the learning style and other parameters of each student. By using a library of micromodules worked out specifically for different learning styles, the Custom Course Compiler is able to assemble different versions of a course, customized for each learner. The paper describes the design, the development, and the structure of the Course Compiler, the connection with the micromodule database, and the underlying pedagogical organization. The operation of the compiler is based on metadata used to classify content and pedagogical parameters of learning units. The design environment includes tools to facilitate the cooperation among several authors, working on similar contents but with different teaching styles, the reuse of existing material, and the verification of the prerequisite-con tents chain.

Design Solutions for a University Nano-satellite

Many universities are now involved in projects related to design, assembly, and operation of small satellites. These projects, with participation of researchers and students, and support of external companies, do not aim to compete with commercial satellites; the main goal is to increase the experience level which contributes to make space applications affordable also to small organizations. For students, participation in the complete process of satellite design, assembly, and testing, offers a unique experience within an interdisciplinary complex project. External companies are involved in creating a community of researchers focused on space applications, thus creating new markets and opportunities. The paper describes the architecture and design solutions of a small satellite developed at Politecnico di Torino in the above mentioned context. The main design goal was to combine the usually conflicting cost and reliability constraints; cost has been limited by using properly selected COTS (commercial off the shelf) devices. Reliability has been achieved through redundancy and design diversity. Focus of the paper is on overall satellite design and architecture, with details of solutions to enhance reliability down to the hardware level. The experience led to the development of a new course (master level) and to several new projects currently under way.

Design Solutions for Modular Satellite Architectures

The cost-effective access to space envisaged by ESA would open a wide range of new opportunities and markets, but is still many years ahead. There is still a lack of devices, circuits, systems which make possible to develop satellites, ground stations and related services at costs compatible with the budget of academic institutions and small and medium enterprises (SMEs). As soon as the development time and cost of small satellites will fall below a certain threshold (e.g. 100,000 to 500,000 €), appropriate business models will likely develop to ensure a cost-effective and pervasive access to space, and related infrastructures and services. These considerations spurred the activity described in this paper, which is aimed at: - proving the feasibility of low-cost satellites using COTS (Commercial Off The Shelf) devices. This is a new trend in the space industry, which is not yet fully exploited due to the belief that COTS devices are not reliable enough for this kind of applications; - developing a flight model of a flexible and reliable nano-satellite with less than 25,000€; - training students in the field of avionics space systems: the design here described is developed by a team including undergraduate students working towards their graduation work. The educational aspects include the development of specific new university courses; - developing expertise in the field of low-cost avionic systems, both internally (university staff) and externally (graduated students will bring their expertise in their future work activity); - gather and cluster expertise and resources available inside the university around a common high-tech project; - creating a working group composed of both University and SMEs devoted to the application of commercially available technology to space environment. The first step in this direction was the development of a small low cost nano-satellite, started in the year 2004: the name of this project was PiCPoT (Piccolo Cubo del Politecnico di Torino, Small Cube of Politecnico di Torino). The project was carried out by some departments of the Politecnico, in particular Electronics and Aerospace. The main goal of the project was to evaluate the feasibility of using COTS components in a space project in order to greatly reduce costs; the design exploited internal subsystems modularity to allow reuse and further cost reduction for future missions. Starting from the PiCPoT experience, in 2006 we began a new project called ARaMiS (Speretta et al., 2007) which is the Italian acronym for Modular Architecture for Satellites. This work describes how the architecture of the ARaMiS satellite has been obtained from the lesson learned from our former experience. Moreover we describe satellite operations, giving some details of the major subsystems. This work is composed of two parts. The first one describes the design methodology, solutions and techniques that we used to develop the PiCPoT satellite; it gives an overview of its operations, with some details of the major subsystems. Details on the specifications can also be found in (Del Corso et al., 2007; Passerone et al, 2008). The second part, indeed exploits the experience achieved during the PiCPoT development and describes a proposal for a low-cost modular architecture for satellites

Hardware Implementations of Artificial Neural Networks

The availability of effective and low-cost neural hardware opens the gate towards applications of neural networks which can compete with other techniques. This paper describes the design problems of silicon neural architectures, and analyzes the various implementations choices. Emphasys in on methodology and principles. Pointers to descriptions of specific neural circuits are provided.

The μ Project: An Experience with a Multimicroprocessor System

Which processor interconnection method makes a modular, reconfigurable system perform best in a given application? Certain tools and strategies help provide the answer.

A 32 Bit Processor for Compiled Prolog

The diffusion of the Logic Programming paradigm in many fields of the Artificial Intelligence requires the design and the implementation of new dedicated machines to improve the execution speed. Among the logic programming languages, Prolog is actually the most widely used. For this reason the realization of efficient Prolog machines represents an essential background for the development of AI techniques.