Daoming Ke

The analysis and modeling of on-resistance in high-voltage LDMOS

An analytical method is proposed in order to compute the on-resistance in high-voltage power device LDMOS with structure of deep n-well and fried plate. With the equivalent series circuit of LDMOS resistance presented, by considering the exponential doping distribution in channel, the channel current equation is modified in this paper. In drift region, the resistance is divided into four components due to doping profiles, current performance and device geometries. Finally, the paper deduced analytic on-resistance expression of LDMOS which agrees with the result obtained from two-dimensional simulation

Capacitance Performance of Single Material Double Workfunction Gate(SMDWG) MOSFET

In this paper, Single Material Double Workfuntion Gate (SMDWG) MOSFET was proposed, which is compatible with CMOS technology and has the performance as Dual Material Gate(DMG) MOSFET. The capacitance performance of SMDWG MOSFET is simulated by MEDICI. Comparison with p+ gate and n+ gate MOSFET are made, and the differences are discussed in detail. The SMDWG MOSFET device operating at subthreshold state is suggested to be used in analog ICs.

A new dual-material gate LDMOS for RF power amplifiers

In this paper, a novel silicon RF lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) structure, using an effective concept of dual-material gate (DMG), is proposed. The gate of the DMG-LDMOS consists of S-gate (the first gate approaching source with high workfunction material p+ poly) and D-gate (the second gate approaching drain with low workfunction material n+ poly). The MEDICI simulations reveal that the DMG-LDMOS can reduce the peak electric field of drain, enhance transconductance and breakdown voltage, which result in a more rapidly acceleration of carriers in the channel and a screening effect to suppress hot carrier effects

Temperature Characteristics for Threshold Voltage of HV LDMOS

The temperature characteristics (at -27degC-300degC) on high voltage power LDMOS are discussed, and a calculation formula of threshold voltages temperature coefficient is given in this paper. Computing results show that the threshold voltage temperature coefficient of a high voltage power LDMOS is a constant in a wide range of temperature, a linear expression can be used to describe its temperature characteristics, and the threshold voltage temperature coefficient can be decreased by thin gate oxide film and high channel doping concentration

A Compact Equivalent Circuit Model of HVLDMOS and Application in HIVC Design

In this paper, a novel equivalent circuit of high voltage LDMOS is presented, which can be embedded into SPICE and applied in high voltage integrated circuits design. Compared with the conventional circuit models of LDMOS, this model does not divide the on-state region of LDMOS into a linear region and a saturation region. Consequently, the formulas for the circuit model contain fewer parameters easily extracted. This paper first creates an I-V equation which is not only available in the on-state region but also suitable to the sub-threshold region based on numerical simulation, and then we obtain a very simple equivalent circuit. The method of parameters extraction in the model is also offered in details. In the end we give an application of designing a CMOS inverter and verify it by MEDICI

Analysis of High Voltage LDMOS Power Consumption

According to the high voltage LDMOS macromodel established in previous work, the inverter consists of LDMOS with high resistance drift region was analyzed. A formulation was presented to solve the power consumption of LDMOS power integrated circuits. The results are shown in good agreement with the simulation values by the two-dimensional numerical simulator MEDICI. Finally, a method to reduce circuit power consumption was presented.

Effective Mobility in Nano-Scaled n-MOSFETs

In this work, we present a methodology for calculating mobility of nano-scaled MOSFETs from the Boltzmann transport equation (BTE). Approximate solution of the BTE for electrons in nano-scaled MOSFETs is given, and the improved distribution function of the carriers is used to model the mobility of carriers. A new model is presented for two-dimensional characteristic field-dependent mobility. Comparing the theoretical curves with an extensive set of simulation ones has validated this model

Correction in Threshold Voltage Model Accounting for Quantum Effects in Strong Inversion Channel

Based on the improved approximation of modified triangular potential well, a physical-based model of MOSFETs threshold voltage as well as its analytical formulation, considering quantum effects in strong inversion layer, is presented. The new model accounts for quantum effects for future generation MOS devices and integration circuits. The calculated results of the improved model obtained from this work were found to be in good agreement with 1D threshold voltage in sub-50nm device, comparing with classical results

Polysilicon Gate Quantum Effect Model for nanoscale MOSFET's

A novel polysilicon gate quantum effect model for MOSFET devices is presented. Only two fitting parameters are required to account for the polysilicon gate quantum effects. It is shown that neglecting the polysilicon gate quantum effects for nanoscale MOSFETs may lead to a lager error in gate capacitance. Comparing with the Medici simulated results validates the model

Physics-based Modeling and Simulation of Dual Material Gate(DMG) LDMOS

In this paper, an analytical modeling of a new structure called dual material gate (DMG) lateral double diffused metal oxide semiconductor (LDMOS) is presented, which combines the advantages of LDMOS and DMG MOSFET. The expressions for the surface potential and electric field under the two poly-silicon gates are derived. Then, a modeling strategy for channel current is presented for the DMG-LDMOS. Channel current model includes the velocity overshoot effect, and avoids calculating the nonlinear drift resistance which is prohibitively difficult to value for LDMOS. The model results are verified by comparing them to simulated results obtained from the device simulator MEDICI