Junning Chen

A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier

A novel cascade control replica bitline delay (CCRBD) technique has been proposed to reduce timing process-variation of SRAM sense amplifier in this brief. The main idea of this technique is that both replica bitlines (RBLs) are utilized, and one is cascade controlled by the other. Simulation results show that the timing process-variation of this technique decreases by 41.83% compared with conventional strategy. Simultaneously, the cycle time is also reduced by 19% at the supply voltage of 800mV in TSMC 65 nm technology. Additionally, the area of the proposed scheme is nearly the same as that with conventional replica bitline technique.

Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier

A resilient tracking circuit for suppressing the timing variation of SRAM sense amplifier enable (SAE) signal is proposed. Pipelined replica bitline technique is used to favour the desired design. Simulation results show that the cycle time is reduced by ∼27% owing to ∼70% reduction of the standard deviation of SAE at a 1.05V supply voltage in 28 nm CMOS technology with four-stage pipeline.

A compact model for single material double work function gate MOSFET

An analytical surface potential model for the single material double work function gate (SMDWG) MOSFET is developed based on the exact resultant solution of the two-dimensional Poisson equation. The model includes the effects of drain biases, gate oxide thickness, different combinations of S-gate and D-gate length and values of substrate doping concentration. More attention has been paid to seeking to explain the attributes of the SMDWG MOSFET, such as suppressing drain-induced barrier lowering (DIBL), accelerating carrier drift velocity and device speed. The model is verified by comparison to the simulated results using the device simulator MEDICI. The accuracy of the results obtained using our analytical model is verified using numerical simulations. The model not only offers the physical insight into device physics but also provides the basic designing guideline for the device.

Physical mechanism of resistance switching in the co-doped RRAM

The physical mechanism of the resistance switching for RRAM with co-doped defects (Ag and oxygen vacancy) is studied based on the first principle calculations and the simulation tool VASP. The interaction energy, formation energy and density of states of Ag and oxygen vacancy defect (VO) are calculated. The calculated results reveal that the co-doped system is more stable than the system only doped either Ag or VO defect and the impurity energy levels in the band gap are contributed by Ag and VO defects. The obtained partial charge density confirmed further that the clusters are obvious in the direction of Ag to Hf ions, which means that it is Ag but VO plays a role of conductive paths. For the formation mechanism, the modified electron affinity and the partial charge density difference are calculated. The results show that the ability of electron donors of Ag is stronger than Vm O In conclusion, the conductivity of the physical mechanism of resistance switching in the co-doped system mainly depends on the doped Ag.

A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process

With advances in semiconductor technology, the threshold voltage variation has worsened, which has a great impact on the speed and stability of static random access memory (SRAM). This paper proposes a pipeline replica bitline (RBL) delay technique designed to reduce the timing variation of SRAM sense amplifiers. This design takes full advantage of all cells in the RBL as replica cells (RCs). A tunable pipeline structure is applied to control the discharge of groups of RCs. The structure is designed based on theoretical analysis and fabricated using an SMIC 28-nm CMOS process. The measurement results show that the delay variation can be reduced by approximately 43% and 32% compared with the conventional RBL and multistage RBL, respectively. Furthermore, with slight tuning of the normal 28-nm foundry process, four wafers were obtained under extreme conditions to comprehensively test the proposed technique. The results show that the proposed technique is more stable than other techniques in any extreme condition.

An Improved SAR Controller for ADDLL Used in DVFS System

An improved successive approximation register (SAR) controller for all digital delay-locked loops (ADDLLs) is proposed to overcome the dead lock problem of the conventional SAR controller by embedding a restarting circuit module into the conventional SAR controller. The ADDLL that adopts the new SAR controller can track the operating frequency variation after the first lock-in, keep the advantages of the SAR searching algorithm and satisfy the requirements of DVFS systems.

The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

An Improved Phase Comparator for the Fast-Locking All Digital SARDLL

An improved phase comparator solution for the fast-locking all digital SARDLL, which can deal with the irregular clock signal and give the signal Comp reflecting the phase relations between input clock and output clock, and the signal LD indicating whether the DLL is locked or not, is presented. The improved solution is justified by the transistor- level post-layout SPICE simulation results.

Process Antenna Effect Elimination in Ultra Deep Submicron

This paper analyzes the mechanism of process antenna effect in ultra deep submicron IC physical design and provides the antenna ratio calculation method. A new elimination method of process antenna effect combined with clock tree synthesis is proposed. The elimination method minimizes the impact to the clock latency and clock skew by setting up reasonable constraint for clock tree synthesize. Finally, the elimination method is used during place and route of the physical design of a reconfigurable video decoder chip, which is based on TSMC 65nm low power technology. The proposed method eliminates the process antenna effect of the design effectively, also minimizes the impact to clock tree and chip timing to the least.

A Digitally Controlled Oscillator for ADPLL Application

In order to solve the defects in performance for analog RF circuit in deep submicron process, this paper discusses a new type of LC oscillators(Digitally Controlled Oscillator), which uses digital RF method to achieve the technology requirements of wireless communication. This new type of oscillator uses MOS varactor arrays to moderating the output frequency, through the using of digitally Sigma-Delta technology, we can get more precise resolution , and through using three modes progressively working way can make this kind of structure easily implement in process.