Dario Gil

Benefits and trade-offs of global source optimization in optical lithography

Source optimization in optical lithography has been the subject of increased exploration in recent years [1-4], resulting in the development of multiple techniques including global optimization of process window [4]. The performance advantages of source optimization have been demonstrated through theory, simulation, and experiment. This paper will emphasize global optimization of sources over multiple patterns, e.g. co-optimization of critical SRAM cells and the critical pitches of random logic, and implement global source optimization into current resolution enhancement techniques (RETs). The effect on optimal source due to considering multiple patterns is investigated. We demonstrate that optimal source for limited patterns does work for a large clip of layout. Through theoretical analysis and simulations, we explain that only critical patterns and/or critical combinations of patterns determine the final optimal source; for example those patterns that contain constraints which are active in the solution. Furthermore, we illustrate, through theory and simulation, that pixelated sources have better performance than generic sources and that in general it is impossible for generic sources to construct a truly optimal solution. Sensitivity, tool matching, and lens heating issues for pixelated sources are also discussed in this paper. Finally, we use a RETs example with wafer data to demonstrate the benefits of global source optimization.

32 NM LOGIC PATTERNING OPTIONS WITH IMMERSION LITHOGRAPHY

The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. These techniques have been successfully employed for early 32nm node development using 45nm generation tooling. Four different double patterning techniques were implemented. The first process illustrates local RET optimization through the use of a split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging properties and the illumination conditions for each are independently optimized. These regions are then printed separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging with particular focus on both line-end dimension and linewidth control [1]. A double exposure-double etch (DE2) approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process, optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay tolerant [6]. Collectively, the double patterning solutions developed for early learning activities at 32nm can be extended to 22nm applications.

Progress toward developing high performance immersion compatible materials and processes

To make immersion lithography a reality in manufacturing, several challenges related to materials and defects must be addressed. Two such challenges include the development of water immersion compatible materials, and the vigorous pursuit of defect reduction with respect to both the films and the processes. Suitable resists and topcoats must be developed to be compatible with the water-soaked environment during exposure. Going beyond the requisite studies of component leaching from films into the water, and absorption of water into the films, application-specific optimization of photoresists and top coats will be required. This would involve an understanding of how a wide array of resist chemistry and formulations behave under immersion conditions. The intent of this paper is to compare lithographic performance under immersion and dry conditions of resists containing different polymer platforms, protecting groups, and formulations. The compatibility of several developer-soluble top-coat materials with a variety of resists is also studied with emphasis on profile control issues. With respect to defects, the sources are numerous. Bubbles and particles created during the imaging process, material remnants from incomplete removal of topcoats, and image collapse as related to resist swelling from water infusion are all sources of yield-limiting defects. Parallel efforts are required in the material development cycle focusing both on meeting the lithographic requirements, and on understanding and eliminating sources of defects. In this paper, efforts in the characterization and reduction of defects as related to materials chemistry and processing effects will be presented.

A computational technique to optimally design in-situ diffractive elements: applications to projection lithography at the resist resolution limit

Near-field interference lithography is a promising variant of multiple patterning in semiconductor device fabrication that can potentially extend lithographic resolution beyond the current materials-based restrictions on the Rayleigh resolution of projection systems. With H2O as the immersion medium, non-evanescent propagation and optical design margins limit achievable pitch to approximately 0.53λ/nH2O = 0.37λ. Non-evanescent images are constrained only by the comparatively large resist indices (typically1.7) to a pitch resolution of 0.5/nresist (typically 0.29). Near-field patterning can potentially exploit evanescent waves and thus achieve higher spatial resolutions. Customized near-field images can be achieved through the modulation of an incoming wavefront by what is essentially an in-situ hologram that has been formed in an upper layer during an initial patterned exposure. Contrast Enhancement Layer (CEL) techniques and Talbot near-field interferometry can be considered special cases of this approach. Since the technique relies on near-field interference effects to produce the required pattern on the resist, the shape of the grating and the design of the film stack play a significant role on the outcome. As a result, it is necessary to resort to full diffraction computations to properly simulate and optimize this process. The next logical advance for this technology is to systematically design the hologram and the incident wavefront which is generated from a reduction mask. This task is naturally posed as an optimization problem, where the goal is to find the set of geometric and incident wavefront parameters that yields the closest fit to a desired pattern in the resist. As the pattern becomes more complex, the number of design parameters grows, and the computational problem becomes intractable (particularly in three-dimensions) without the use of advanced numerical techniques. To treat this problem effectively, specialized numerical methods have been developed. First, gradient-based optimization techniques are used to accelerate convergence to an optimal design. To compute derivatives of the parameters, an adjoint-based method was developed. Using the adjoint technique, only two electromagnetic problems need to be solved per iteration to evaluate the cost function and all the components of the gradient vector, independent of the number of parameters in the design.