Darsen D. Lu

Modeling Advanced FET Technology in a Compact Model

The need for meeting the expectations of continuing the enhancement of CMOS performance and density has inspired the introduction of new materials into the classical single-gate bulk MOSFET and the development of nonclassical multigate transistors at an accelerated rate. There is a strong need to understand and model the associated new physics and electrical behavior to ensure widespread very-large-scale-integration circuit applications of new technologies. This paper presents some of the efforts toward the modeling of new technologies for bulk MOSFETs and multigate transistors. A holistic model for mobility enhancement through process-induced stress and a dynamic behavior model for high-k transistors have been developed to capture some of the new effects and new materials in the bulk MOSFET. A new analytical model is also presented for the fundamentally new device structure-FinFET

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.

BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design

A novel surface-potential based multi-gate FET (MG-FET) compact model has been developed for mixed-signal design applications. For the first time, a MG-FET model captures the effect of finite body doping on the electrical behavior of MG-FETs. A unique field penetration length model has been developed to model the short channel effects in MG-FETs. A multitude of physical effects such as poly-depletion effect and quantum-mechanical effect (QME) have been incorporated. The expressions for terminal currents and charges are co-continuous making the model suitable for mixed-signal design. The model has been verified extensively with TCAD and experimental data.

A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation

A compact model for multi-gate MOSFETs with two independently-biased gates is presented. The core model is verified against TCAD simulations without the use of any fitting parameters. Real device effects such as short channel effects and body doping effects are captured. The use of the model is demonstrated through two simulation examples: (1) Back-gate dynamic feedback of FinFET SRAM cells and (2) Tuning of device variations through back gate biasing.

Design of FinFET SRAM Cells Using a Statistical Compact Model

A study of designing FinFET-based SRAM cells using a compact model is reported. Parameters for a multi-gate FET compact model, BSIM-MG are extracted from fabricated n-type and p-type SOI FinFETs. Local mismatch in gate length and fin width is calibrated to electrical measurements of 378 FinFET SRAM cells. The cell design is re-optimized through Monte Carlo statistical simulations. Variation in readability, writability and static leakage of the cell are studied.

Performance-Aware Corner Model for Design for Manufacturing

We present a methodology to generate performance-aware corner models (PAMs). Accuracy is improved by emphasizing electrical variation data and reconciling the process and electrical variation data. PAM supports corner (plusmnsigma and plusmn 2sigma) simulation and Monte Carlo simulation. Furthermore, PAM supports the practice of application-specific corner cards, for example, for gain-sensitive applications.

Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs

In this letter, we present a thermal network extraction methodology to characterize self-heating effect using two-port RF measurements. We show the technique of determining isothermal condition using only the self-heating (thermal) dominated range of the spectrum. We use a self-consistent self-heating extraction scheme using both the real and imaginary parts of drain port admittance parameters. Appropriate thermal network is investigated, and a large amount of temperature rise due to self-heating is confirmed for short channel silicon-on-insulator MOSFETs with ultrathin body and buried oxide.

Compact Modeling of Variation in FinFET SRAM Cells

FinFET technology is a possible solution to achieve a better power/performance trade-off for SRAM cells. This article provides a comprehensive analysis of the variations in FinFET devices, their impact on SRAM stability, and a statistical design procedure for FinFET SRAM cells.

Compact modeling of flicker noise variability in small size MOSFETs

A compact model has been developed to capture the variability of flicker noise resulting from the reduction in size of state of the art MOSFETs. The underlying physics of flicker noise in small area MOSFETs has been verified by two means: Monte Carlo simulation and analytic modeling. The statistical distribution of flicker noise is reported for the first time, supported by experimental data from two sets of devices with different areas. The developed model is capable of predicting the area dependence of noise at any frequency at desired %Yield.

Global parameter extraction for a multi-gate MOSFETs compact model

A global I-V parameter extraction methodology for multi-gate MOSFET compact model is presented for the first time. New L-dependent properties are proposed to enable the accurate modeling of transistors over a wide range of gate length using a single set of model parameters. The results are verified with FinFET experimental data with effective channel lengths from 30nm to 10um. For both n and p type devices, excellent agreement between the data and the model has been demonstrated.