Bruce B. Doris

Extreme scaling with ultra-thin Si channel MOSFETs

We examine the scaling limits for planar single gate technology using the ultra-thin Si channel MOSFET. Characteristics for extreme scaled devices with physical gate lengths down to 6 nm and SOI channels as thin as 4 nm are presented. For the first time, we report ring oscillators with 26 nm gate lengths and ultra-thin Si channels.

A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates

Threshold voltage (V_t) of a field effect transistor (FET) is observed to shift with stressing time and this stress induced V _t shift is an important transistor reliability issue. V_t shifts that occur under negative gate bias is referred as NBTI and those that occur under positive bias is referred as PBTI or charge trapping. In this paper, we present a comparative study of NBTI and PBTI for a variety of FETs with different dielectric stacks and gate materials. The study has two parts. In part I, NBTI and PBTI measurements are performed for FUSI NiSi gated FETs with SiO₂ SiO₂/HfO₂ and SiO₂/HfSiO as gate dielectric stacks and the results are compared with those for conventional SiON/poly-Si FETs. The main results are: (i) NBTI for SiO ₂/NiSi and SiO₂/HfO₂/NiSi are same as those conventional SiON/poly-Si FETs; (ii) PBTI significantly increases as the Hf content in the high K layer is increased; and (iii) PBTI is a greater reliability issue than NBTI for HfO₂/NiSi FETs. In part II of the study, NBTI and PBTI measurements are performed for SiO2/HfO2 devices with TiN and Re as gates and the results are compared with those for NiSi gated FETs. The main results are: (i) NBTI for SiO ₂/HfO₂/TiN and SiO₂/HfO₂/Re pFETs are similar with those observed for NiSi gated pFETs; and (ii) PBTI in TiN and Re gated HfO₂ devices is much smaller than those observed for SiO₂/HfO₂/NiSi. In summary for SiO₂/HfO₂ stacks, NBTI is observed to be independent of gate material whereas PBTI is significantly worse for FUSI gated devices. Consequently, HfO₂ FETs with TiN and Re gates exhibit over all superior transistor reliability characteristics in comparison to HfO₂/FUSI FETs

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 µA/µm, respectively, at Ioff = 300 pA/µm, VDD = 0.9V, and LG = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low VT variability is achieved with AVt of 1.25 mV·µm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt -mismatch is discussed for continuous FinFET SRAM cell-size scaling.

Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

We have fabricated electrically reliable band-edge (BE) high-k/metal nMOSFETs stable to 1000degC, that exhibit the highest mobility (203 cm2/Vs @ 1MV/cm) at the thinnest Tinv (1.4 nm) reported to date. These stacks are formed by capping HfO2 with ultra-thin layers containing strongly electropositive gp. IIA and IIIB elements (e.g. Mg and La), prior to deposition of the TiN/Poly-Si electrode stack, in a conventional gate-first flow. Increasing the cap thickness tunes the Vt/V fb from a midgap position to BE while maintaining high mobility and good PBTI. The addition of La can enhance the effective k value of the dielectric stack, resulting in EOTs < 1nm. Short channel devices with band edge characteristics are demonstrated down to 60 nm. Finally, possible mechanisms to explain the nFET Vt shift are discussed

Examination of flatband and threshold voltage tuning of HfO2∕TiN field effect transistors by dielectric cap layers

The authors have examined the role of sub nanometer La2O3 and LaN cap layers interposed in Si∕HfO2∕TiN high-k gate dielectric stacks in tuning the flatband and threshold voltages of capacitors and transistors. High performance, band edge n metal oxide field effect transistors with channel lengths down to 60nm may be fabricated without significant compromise in mobility, electrical thickness, and threshold voltage. They have carried out a microstructural evaluation of these stacks and correlated these results with the electrical behavior of the devices.

A 0.063 µm 2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

We demonstrate the smallest FinFET SRAM cell size of 0.063 µm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic V<inf>T</inf>-variability performances are obtained (A<inf>VT</inf>=1.45mV.µm). This leads to 6T-SRAM cells with good characteristics down to V<inf>DD</inf>=0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σ<inf>SNM</inf><SNM/6) down to V<inf>DD</inf>=0.7V. We also demonstrate ultra-low leakage (<0.5pA/µm) on UT2B devices at L<inf>G</inf>= 30nm by source/back biasing thanks to a low gate current and Gate Induced Drain Lowering (GIDL).

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12Å) for BE nFET devices to-date, consistent with simulations showing the need for ≪14Å Tinv at Lgate≪35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFETs fabricated with gate-first high thermal budget processing with thin Tinv (≪13Å) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFETs into CMOS devices yielded large SRAM arrays.

22 nm technology compatible fully functional 0.1 μm 2 6T-SRAM cell

We demonstrate 22 nm node technology compatible, fully functional 0.1 mum2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at Vdd=0.9 V. We also present a 0.09 mum2 cell with SNM of 160 mV at Vdd=0.9 V demonstrating the scalability of the design with the same layout. This is the worlds smallest 6T-SRAM cell. Key enablers include band edge high-kappa metal gate stacks, transistors with 25 nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.