Kern Rim

Six-band k⋅p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness

A six-band k⋅p model has been used to study the mobility of holes in Si inversion layers for different crystal orientations, for both compressive or tensile strain applied to the channel, and for a varying thickness of the Si layer. Scattering assisted by phonons and surface roughness has been accounted for, also comparing a full anisotropic model to an approximated isotropic treatment of the matrix elements. Satisfactory qualitative (and in several cases also quantitative) agreement is found between experimental data and theoretical results for the density and temperature dependence of the mobility for (001) surfaces, as well as for the dependence of the mobility on surface orientation [for the (011) and (111) surfaces]. Both compressive and tensile strain are found to enhance the mobility, while confinement effects result in a reduced hole mobility for a Si thickness ranging from 30 to 3 nm.

Measurement of the effect of self-heating in strained-silicon MOSFETs

The self-heating of strained-silicon MOSFETs is demonstrated experimentally. Output characteristics measured by a pulse technique, in which self-heating is absent, show as much as 15% greater drain current (for 15% Ge content) than the corresponding static measurements. Comparison of the current measured this way with the static measurements allows an estimate of the channel temperature during the static operation. The temperature rise is compared to a simple estimate of the thermal resistance of the FET.

Transistor Mismatch Properties in Deep-Submicrometer CMOS Technologies

Transistor mismatch data and analysis from poly/SiON and high-k/metal-gate (HKMG) bulk CMOS technologies are presented. It is found that the traditional mismatch figure of merit from the Pelgrom plot (AVT) continuously scales down as technology advances. Furthermore, the AVT values for both nFET and pFET in the HKMG technology are significantly reduced from poly/SiON technologies. By normalizing the mismatch data against electrical oxide thickness (TINV) , threshold voltage (VTH), and effective work function, a direct comparison of the mismatch data from various technologies is made. The differences in nFET and pFET mismatch behaviors in both poly/SiON and HKMG technologies are discussed in detail. Correlation between transistor VTH mismatch and flicker noise variation is observed in both poly/SiON and HKMG technologies. Finally, it is quantitatively demonstrated that effective work function variation does not generate significant VTH variability in the present HKMG technology.

Electrical characterization of Al 2 O 3 n-channel MOSFETs with aluminum gates

High-effective mobilities are demonstrated in Al/sub 2/O/sub 3/ based n-channel MOSFETs with Al gates. The Al/sub 2/O/sub 3/ was grown in ultra-high vacuum using a reactive atomic beam deposition system. The mobility with maximum values at approximately 270 cm/sup 2//Vs, is found to approach that of SiO/sub 2/ based MOSFETs at higher fields.

Aggressively scaled strained silicon directly on insulator (SSDOI) FinFETs

Strain engineering has been in the heart of CMOS technology for over a decade. However, the effectiveness of conventional strain elements, such as stress liners, embedded S/D stressors, and stress memorization, is significantly reduced when device gate pitch is scaled below 100 nm as needed for 14nm node and beyond. Substrate strain engineering, where the channel itself is formed out of a strained semiconductor, e.g. in the form of strained silicon directly on insulator (SSDOI) or strained SiGe-on-insulator has the advantage that the strain is independent of the device pitch or gate length as long as the active region is made sufficiently long and the strain is maintained throughout the device processing. We have already shown that in a FinFET structure the starting biaxial strain in the SSDOI substrate is converted to a more beneficial uniaxial strain, strain can be maintained throughout typical thermal processing, and demonstrated roughly 15% increase in NFET performance in deeply scaled FinFETs. However, this is still far less than the performance gain we reported recently in ETSOI devices. In this work, for the first time we report NFET performance gain in SSDOI FinFETs fabricated with contacted gate pitch (CGP) down to 64nm.