Hai Jiang

Experimental investigation of self heating effect (SHE) in multiple-fin SOI FinFETs

In this work, the self-heating effect (SHE) on metal gate multiple-fin SOI FinFETs is studied by adopting the ac conductance technique to extract the thermal resistance and temperature rise in both n-channel and p-channel SOI FinFETs with various geometry parameters. It is shown that the SHE degrades by over 10% of the saturation output current in the n-channel and by over 7% in the p-channel. The extracted thermal resistances Rth increase with the scaled down gate length, reducing the number of fin and shrinking the fin width. The temperature rise caused by the SHE increases with the scaled down gate length, increasing the number of fin and shrinking the fin width under the saturated operation condition. Additionally, due to a larger power density in the n-channel SOI FinFETs under the same bias condition, the temperature in the n-channel FinFETs is higher than that in the p-channel FinFETs. Because the Si thermal conductivity decreases as the temperature increases, Rth is larger in the n-channel FinFETs than in the p-channel FinFETs. Therefore, tradeoffs have to be made between the thermal properties and the device’s electrical performance by careful design optimizations of SOI FinFETs.

Investigation of Self-Heating Effect on Hot Carrier Degradation in Multiple-Fin SOI FinFETs

In this letter, the impact of self-heating effect (SHE) on hot carrier degradation (HCD) in multiple-fin silicon-on-insulator (SOI) FinFETs was investigated. First, the ac conductance method has been utilized to extract the thermal resistance (Rth) of SOI FinFETs with different fin numbers. Then, both dc and ac stresses are applied on the gate and drain of transistors with the source grounded to characterize the HCD. It is found that the device with large fin number demonstrates high-temperature rise caused by SHE, which results in the enhanced generation of oxide bulk trapped charges. Thus, the SHE aggravates the HCD significantly. The influence of SHE on HCD is mitigated when the frequency of ac stress is above 10 MHz. Therefore, special attention to the SHE on HCD must be paid for accurate HCD prediction in FinFETs.

Comprehensive understanding of hot carrier degradation in multiple-fin SOI FinFETs

In this work, we comprehensively explore hot carrier degradation (HCD) in multiple-fin SOI FinFETs with both short channel length and long channel length, and demonstrate that the degradation mechanism in short channel device is different from that of long channel device. The hot carrier degradation in short channel length device under long stress time is dominated by oxide charge. Meanwhile, the hot carrier degradation is aggravated by self-heating effect (SHE).

Impact of self-heating effects on nanoscale Ge p-channel FinFETs with Si substrate

In this paper, self-heating effects (SHE) in nanoscale Ge p-channel FinFETs with Si substrate are evaluated by TCAD simulation. Hydrodynamic transport with modified mobilities and Fourier´s law of heat conduction with modified thermal conductivities are used in the simulation. Ge p-channel single-fin FinFET devices with different S/D extension lengths and fin heights, and multi-fin FinFETs with different fin numbers and fin pitches are successively investigated. Boundary thermal resistances at source, drain and gate contacts are set to 2000 μm2K/W and the substrate thermal boundary condition is set to 300 K so that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below: (i) 14 nm Ge p-channel single-fin FinFETs with a 47 nm fin pitch experience 9.7% on-state current degradation. (ii) Considering the same input power, FinFETs with a longer S/D extension length show a higher lattice temperature and a larger on-state current degradation. (iii) Considering the same input power, FinFETs with a taller fin height show a higher lattice temperature. (iv) The temperature in multi-fin FinFET devices will first increase then saturate with the increasing fin number. At last, thermal resistances in Ge p-channel single-fin FinFETs and multi-fin FinFETs are investigated.

Unified self-heating effect model for advanced digital and analog technology and thermal-aware lifetime prediction methodology

Self-heating effect (SHE) has become a significant concern for device performance, variability and reliability co-optimization due to more confined layout geometry and lower-thermal-conductivity materials adopted in advanced transistor technology, which substantially impacts the integrated circuit (IC)s design schemes. In this work, a new methodology for evaluation of SHE in both digital and analog circuits is demonstrated by using pulse-aware and existing sine-aware analytical models respectively. Correlating SHE to physics-based thermal-aware reliability models provides insights for design and sign-offs of advanced digital and analog ICs.

Investigation of local heating effect for 14nm Ge pFinFETs based on Monte Carlo method

FinFET is regarded as one of the most promising device structure for future scaling-down demands. However, heat dispassion is a severe problem for the device performance and reliability in nano-scale FinFETs. Germanium (Ge) is a novel channel material with its high carrier mobility, especially for PMOSFET. However, the bulk thermal conductivity of Ge (52.98Wm-1K-1) is almost 3 times smaller than that of Si (148.6Wm-1K-1)[1], which will lead to more serious heat dispassion problems in Ge devices. Whats more, the phonon mean free path is largely decreased in nano-device structure due to increased surface scatterings, which leads to a largely reduced thermal conductivity. Hence, heat dissipation problems will have a large impact on the performance of Ge FinFETs. In this paper, we use 3D Full Band Self-consistent Ensemble Monte Carlo Simulator and 3D Fourier Heat Conduction Solver to study the local heating effects (LHE) and its impact on 14nm Ge SOI pFinFETs. The heat dissipation path is also evaluated. From the simulation results, we find that 14nm Ge SOI FinFETs will experience severe heating problems and heat effects will seriously affect the device performance.

Insight into PBTI in InGaAs nanowire FETs with Al 2 O 3 and LaAlO 3 gate dielectrics

The traps induced degradation of the Al<inf>2</inf>O<inf>3</inf> and LaAlO<inf>3</inf> based InGaAs nanowire FETs are investigated by 3D Kinetic Monte-Carlo (KMC) method considering trap coupling and trap generation. The measurement time constants of the defect in Al<inf>2</inf>O<inf>3</inf> and positive bias temperature instability (PBTI) can be well interpreted by consideration with metastable state. The power law of threshold shift can be greatly affected by the stress. Different from traps in Al<inf>2</inf>O<inf>3</inf>, oxygen vacancies and interstitial Aluminum ions in LaAlO<inf>3</inf> have important roles in PBTI. Simulated results indicate that Al<inf>2</inf>O<inf>3</inf> have better PBTI and recovery than that of LaAlO<inf>3</inf>.

Evaulation the degradation in nMOSFETs with HfO 2 gate dielectric and interfacial layer by 3D Kinetic Monte-Carlo method

This paper evaluates the degradation process in nMOSFETs with HfO2 gate dielectric and interfacial layer (IL) by 3D Kinetic Monte-Carlo (KMC) method considering multi-trap coupling. The degradation and corresponding trap evolution in a 1-nm EOT dielectric stack with different thicknesses of SiO2 IL is simulated under different gate biases (Vg) and temperature (T). The results indicate that IL can suppress the positive bias temperature instability (PBTI) but increase the gate leakage and weaken the capability to endure stress.

Reliability investigation of high-k/metal gate in nMOSFETs by three-dimensional kinetic Monte-Carlo simulation with multiple trap interactions

Degradation behaviors in the high-k/metal gate stacks of nMOSFETs are investigated by three-dimensional (3D) kinetic Monte-Carlo (KMC) simulation with multiple trap coupling. Novel microscopic mechanisms are simultaneously considered in a compound system: (1) trapping/detrapping from/to substrate/gate; (2) trapping/detrapping to other traps; (3) trap generation and recombination. Interacting traps can contribute to random telegraph noise (RTN), bias temperature instability (BTI), and trap-assisted tunneling (TAT). Simulation results show that trap interaction induces higher probability and greater complexity in trapping/detrapping processes and greatly affects the characteristics of RTN and BTI. Different types of trap distribution cause largely different behaviors of RTN, BTI, and TAT. TAT currents caused by multiple trap coupling are sensitive to the gate voltage. Moreover, trap generation and recombination have great effects on the degradation of HfO2-based nMOSFETs under a large stress.

Simulation of Positive Bias Temperature Instability (PBTI) in high-k FinFET by KMC method

Positive Bias Temperature Instability (PBTI) of HfO2/metal gate n-channel bulk FinFET is simulated through a KMC method, which includes fully coupled multi-physical models under a unified framework. PBTI is simulated using electron capture/emission and trap generation/recombination. By comparing PBTI of different traps with/without generation and recombination in HfO2, it indicates that the only consideration of trap generation can result in overestimation of the threshold shift and shorten predicted lifetime.