Michael A. Lamson

Multichip assembly with flipped integrated circuits

A multichip module process has been developed using flipped-chip interconnection. The process uses plated copper bumps for superior thermal transport characteristics, active silicon as a substrate material for matched expansion properties, on-chip interconnection metallization that allows bumps to be placed over the active circuitry, and conventional wafer fabrication facilities for low-cost production. For successful design and fabrication of multichip assemblies, an organized methodology similar to that which has proved successful in design and assembly of single VLSI circuits was used. This approach involves: computer-aided modeling of the circuit and package for electrical, thermal, and mechanical simulation; test chips for process development and failure mechanism testing; and fabrication of actual demonstration circuits. Verification of function and reliability was then made through temperature cycle testing (-65 degrees C to 150 degrees C), exposure to accelerated moisture environments, and measure of heat dissipation properties. This approach and an example of its application to a multichip module that demonstrated successful performance on the first design pass are described. >

Lead-on-chip technology for high performance packaging

The modeling and simulation efforts for the development of a lead-over-chip (LOC) style package for 16 Mb dynamic random access memories is described. Electrical models and simulation address the effects of power bus noise and the interaction of chip conductors with the LOC lead frame. The thermomechanical stress issues in the LOC package are modeled using finite element techniques to optimize the design and material properties to avoid damage to the chip or package during fabrication and testing. For surface mount components, stress from the reflow process resulting from vapor pressure concentrated at points of delamination must also be comprehended and minimized. Thermal analysis of the LOC package was performed using finite element analysis and measurements, and the data were compared to those of standard packaging designs.<<ETX>>

Test Chip Electrical Measurements with Model Correlation

An integrated circuit device developed through a JEDEC standards committee with multiple, selectable, and controllable CMOS output drivers is installed in a complex plastic ball grid array package with multiple power and ground planes. A specialized circuit board is designed and used to mount the package and loads, to facilitate device control from an external signal source, and to provide output measurement ports. Measurements of simultaneous switching noise (SSN) are made under various conditions of the test chip operation, measurement points, and ground port configurations. The switching characteristics of the output drivers are shown to depend on the configuration of the package connections and the number of active outputs. Computer models of the system were generated and the data are compared to the measured values. Good correlation with models is observed to be highly dependant on using accurate driver switching characteristics.

An active crosstalk reduction technique for parallel high-speed links in low cost wirebond BGA packages

We report a 4-channel 8 Gb/s/channel transmitter test chip assembled in a low cost 4-layer wirebond BGA package to evaluate the impact of active cross-talk mitigation and equalization techniques on signal performance. A half-rate 4-tap feed-forward and a cross-talk induced jitter equalizer is used to compensate package interconnect losses and data dependent signal coupling, respectively. All coefficients of the FFE and crosstalk jitter equalizer have programmable polarity and magnitude. The chip power dissipation is 225 mW, or 7 mW/Gb/s. The FFE and jitter equalizer achieves a measured RMS jitter reduction of 7.5-ps for an improvement of 50%.

A coaxial probe system for measuring Z-direction electrical resistivity of conductive polymers

A novel coaxial Kelvin probe technique has been developed to measure the z-axis electrical resistivity of conductive polymer adhesives. The approach uses a very simple test structure, comprising of a sandwich of the conductive adhesive material between two Copper conductors. The coaxial probe includes an outer region through which the current is forced, and an inner probe which senses the surface voltage drop, and is hooked to a nano-voltmeter to enable micro-ohms resistance measurements with high sensitivity. This is followed by detailed finite element modeling of the sample and probe set-up configuration to extract an accurate value for the effective z-axis resistivity of the conductive adhesive, as well as its bulk and interfacial z-resistivity values. This technique has been demonstrated on two candidate conductive materials as well as solder (as a reference). It has the potential to enable rapid optimization and development of conductive polymer adhesive systems for different interfaces and for various applications.

Electrical modeling of an IC package chip paddle as an integral ground bus

This paper presents an analysis of an IC package chip paddle connected as an active ground bus to conduct ground currents from the chip to the system ground. To generate the electrical models, non-commercial software acquired through various university sources was utilized. The development of associated software to provide efficient input of CAD data base information and output to simulation programs is briefly described. Various paddle designs and the number and placement of ground path bond wires are modeled and simulated and the results presented.