David A. Baglee

Acceleration Factors for Thin Gate Oxide Stressing

Time dependent dielectric breakdown (TDDB) data for 100Å of thermally grown SiO2 has been analyzed using an Eyring model based on thermodynamic free energy considerations. The model describes well the following features of the data: (1) an apparent activation energy which is a function of the stressing electric field and (2) a field acceleration parameter that is a function of temperature. Quantitatively, the model suggests the proper field dependence for the activation energy and the observed temperature dependence of the field acceleration in the 100Å oxide material. The apparent activation energy is found to decrease from > leV at low field stressing (Eb(50%) - Es > 5 MV/cm) to <0.3eV at higher fields Eb(50%)- Es < 3 MV/cm). Also, the field acceleration was found to be approximately 6 decades/MV/cm at room temperature but reduces to 2 decades/MV/cm at 150C.

Building-in reliability: making it work

Aggressive reliability and market-entry demands will require the use of a building-in approach to reliability. The objectives are (1) to review the essential features of this new approach and contrast them with those of the traditional approaches, (2) to identify obstacles in accepting the building-in-reliability approach and suggest ways to overcome them, and (3) to suggest a way to facilitate the implementation of this approach. The approach requires that significant breaks be made from the traditional ways of improving and appraising reliability. The nature of these breaks is discussed in the context of describing the basic elements of the approach of building-in reliability and the obstacles that hinder its adoption. To help visualize how the approach can be implemented, initial steps in making the transition and some specific examples of its use are described.<<ETX>>

Series resistance modeling for optimum design of LDD transistors

The characteristics of lightly doped drain transistors are presented and compared with conventional devices. A technique for modeling these devices is then described. We show that LDD transistors have lower substrate currents resulting in improved reliability. The amount of the reduction depends on the the source/drain resistance, However we show that this resistance can have a large effect on circuit performance and that the trade off between circuit response and substrate currents must be carefully evaluated. This understanding allows us to fabricate circuits with a minimum number of process iterations.

ESD Protection Reliability in 1μM CMOS Technologies

The use of graded drains and silicided diffusions are shown to severely degrade Electrostatic Protection circuits when compared to their performance with traditional processing technology. The impact of each of these process options on the protection circuit sizing and the particular failure modes observed are reported here.

Properties of trench capacitors for high density DRAM applications

Due to increasing levels of integration, it is expected that next generation DRAMs will make use of trench capacitors to minimize the area of a cell. In this paper we examine the properties of oxides grown in trenches and compare them with comparable oxides grown on planar surfaces. We also examine the effects of various cell to cell spacing on the trench to trench leakage. We conclude that despite the challenges of trench technology, it is excellent for use in 1Mbit and 4Mbit DRAMS.

Chapter 4 - Ultrathin-Gate Dielectric Processes for VLSI Applications

Publisher Summary This chapter describes ultrathin-gate dielectric processes for very large scale integration (VLSI) applications. It discusses the methods for growing thin oxides in the sub-200-A range and also describes the electrical characteristics of these films. The standard manufacturing process for gate oxides has been a 1000°C, dry O2 process with a small amount of HCl added. The amount of HCl added is less than 6%, and its purpose is to neutralize any mobile ionic contamination that may be introduced into the oxide, such as sodium. The oxidation is followed with a high-temperature anneal in an inert ambient, such as argon or nitrogen. High-quality oxides can also be grown with a similar process but with steam replacing the dry O2. The advantage with this technique is that large differential growth rates are obtained between single-crystal substrates and polysilicon layers. This differential is exploited in the manufacture of circuits such as dynamic random access memories.

The Effects of Processing on EEPROM Reliability

EEPROMs have one significant advantage over the more common EPROM. This is in the ease with which data can be changed in just a matter of milliseconds. In this paper we will investigate the effects that the various critical process steps can have on the two key reliability aspects of these memories, namely: Data Retention and Write/Erase endurance. In particular we will examine effects of the tunnel oxidation conditions and protective overcoat type on these parameters.

Scaled LOCOS Processes with Reduced Narrow Width Effects

Scaling of MOS circuits is resulting in transistors exhibiting increased narrow width effects in addition to the usual short channel poblems. In this paper we present a technique for reducing these narrow width effects by using HIPOX to grow the isolation oxide. HIPOX allows us to reduce the channel stop dose, hence reducing moat encroachment, while at the same time maintaining adequate isolation between devices. Data is presented on moat encroachment, thick field transistors and moat diodes as well as a discussion of simulation results. The relationship and trade offs between each of these is examined.

Reliability of Trench Capacitors for VLSI Memories

Trench capacitors will be used in high density memories, such as the 1Mbit or 4Mbit DRAM, in order to minimize the size of the chip. In this paper the properties and reliability of trench capacitors are discussed. We show that the leakage and break-down characteristics are dominated by the trench profile. Accelerated wearout shows that trench capacitors are suitable for 5V operation, and that alpha particle induced soft error rates are similar to, or better than, conventional planar devices.