Michael P. Duane

Lightly doped drain transistors for advanced VLSI circuits

A comprehensive analysis of lightly doped drain (LDD) transistors is presented. We discuss LDD characteristics and ways to model the n-series resistance. This LDD structure has also been found to exhibit greater stability than conventional transistors when subjected to accelerated aging. By analyzing circuits employing both LDD and conventional devices we examine the tradeoffs between circuit performance and long-term circuit stability. We conclude that the fabrication sequence presented for an optimum LDD transistor will result in improved long-term circuit stability with minimal reduction in circuit performance.

An analytical method for determining intrinsic drain/source resistance of lightly doped drain (LDD) devices

Abstract MOS devices with double diffusion junctions containing Lightly Doped Drain/Source (LDD) regions have been built and analyzed. Comparison of current characteristics of the 2 μ m LDD devices with conventional devices of same channel length indicates that the LDD devices, while displaying relatively good drain current gain, deviate from the MOS transistors in the linear region due to the intrinsic n− drain/source resistance and thus have lower substrate current due to the reduced hot electron effects. An analytical method is developed where this intrinsic resistance can be extracted from curve fitting of I–V data. Through curve fitting analysis the intrinsic resistance parameter is found to be an inverse function of transistor width as well as being dependent on temperature in the usual T 3 2 manner.

Scaled LOCOS Processes with Reduced Narrow Width Effects

Scaling of MOS circuits is resulting in transistors exhibiting increased narrow width effects in addition to the usual short channel poblems. In this paper we present a technique for reducing these narrow width effects by using HIPOX to grow the isolation oxide. HIPOX allows us to reduce the channel stop dose, hence reducing moat encroachment, while at the same time maintaining adequate isolation between devices. Data is presented on moat encroachment, thick field transistors and moat diodes as well as a discussion of simulation results. The relationship and trade offs between each of these is examined.

Reduced narrow-width effects in a scaled local oxidation of silicon process

The reduction of narrow-width effects in VLSI transistors is of great importance if small-geometry devices are to be of real use in advanced circuits. These effects are caused by boron encroaching into the transistor channel from underneath the field isolation oxide. In this paper we describe the results of experiments to reduce this encroachment by the use of high-pressure oxidation. We show that the substitution of this process into a VLSI process flow, for the field oxidation step, allows the channel-stop implant dose to be significantly reduced (50%) without degradation of interdevice isolation.