David A. Hodges

Time interleaved converter arrays

An A/D converter technique which uses an array of four 7b converters, with interleaved sampling intervals affording rates exceeding 2MHz, will be covered. A 10μ metal gate CMOS chip is used.

All-MOS charge-redistribution analog-to-digital conversion techniques. II

For pt.I see ibid., vol.SC-10, no.6, p.371-9 (1975). Describes techniques for performing A/D conversion compatibly with standard single-channel MOS technology. This second paper describes a two-capacitor successive approximation technique which, in contrast to the first, requires considerably less die area, is inherently monotonic in the presence of capacitor ratio errors, and which operates at somewhat lower conversion rate. Factors affecting accuracy and conversion rate are considered analytically. Experimental results from a monolithic prototype are presented; a resolution of eight bits was achieved with an A/D conversion time of 100 /spl mu/s. Used as a D/A convertor, a settling time of 12.5 /spl mu/s was achieved. The estimated total die size for a completely monolithic version including logic is 5000 mil/SUP 2/.

Full-speed testing of A/D converters

Improved computer-aided analog-to-digital converter (ADC) characterization methods based on the code density test and spectral analysis using the fast Fourier transform are described. The code density test produces a histogram of the digital output codes of an ADC sampling a known input. The code density can be interpreted to compute the differential and integral nonlinearities, gain error, offset error, and internal noise. Conversion-rate and frequency-dependent behavior can also be measured.

Modeling and simulation of insulated-gate field-effect transistor switching circuits

A new equivalent circuit for the insulated-gate field-effect transistor (IGFET) is described. This device model is particularly useful for computer-aided analysis of monolithic integrated IGFET switching circuits. The results of computer simulations using the new equivalent circuit are in close agreement with experimental observations. As an example of a practical application, simulation results are shown for an integrated circuit IGFET memory cell.

A self-calibrating 15 bit CMOS A/D converter

A self-calibrating analog-to-digital converter using binary weighted capacitors and resistor strings is described. Linearity errors are corrected by a simple digital algorithm. A folded cascode CMOS comparator resolves 30 /spl mu/V in 3 /spl mu/s. An experimental converter fabricated using a 6-/spl mu/m-gate CMOS process demonstrates 15-bit resolution and linearity at a 12-kHz sampling rate.

Nonlinear Echo Cancellation of Data Signals

This paper describes a new technique for implementing an echo canceller for full-duplex data transmission (such as in digital subscriber loops and volceband data sets). The canceller can operate in spite of time-invariant nonlinearities in the echo channel or in the implementation of the echo canceller itself (such as in the D/A converters). The basic structure of the linear echo canceller is not changed, but taps are simply added to account for the nonlinearity. The number of taps which must be added depends on the degree of nonlinearity which must be compensated. Numerical results based on computer simulation are given which show that typical nonlinearities encountered in MOS D/A converters can be compensated by a relatively small number of taps added to the linear echo canceller, and substantial improvement in the cancellation results.

MOS switched-capacitor filters

In the past several years, much progress has been made in bringing the economies of integrated-circuit technology to bear on the realization of voiceband frequency selective filters. This paper will review one approach to this problem, the use of switched-capacitor techniques. The paper emphasizes the practical aspects of switched-capacitor filter design under the constraints imposed by MOS integrated-circuit technology. The basic operation of switched-capacitor filters is reviewed, followed by a discussion of the properties of the various circuit building blocks in MOS technology. Finally, a summary of several filter organizations which appear to be well suited to switched-capacitor implementation is presented.

Design of PLL-based clock generation circuits

The design of clock generation circuitry being used as a part of a high-performance microprocessor chip set is described. A self-calibrating tapped delay line is used to generate four nonoverlapping clock phases of a system clock. A charge-pump phase-locked loop (PLL) calibrates the delay per stage of the delay line. Using this technique, it is possible to obtain an accurate phase relationship between the off-chip reference clock and the internal clock signals. Experimental results show that required timing relations can be obtained with less than 2-ns clock skew for frequencies from 1 to 18 MHz.

A 10-bit 5-Msample/s CMOS two-step flash ADC

A 10-b, 5Msample/s, two-step flash A/D converter fabricated in a 1.6 mu m CMOS process is described. The architecture is based on a resistor string and capacitor arrays and was developed to overcome the disadvantages of the previous approaches, namely flash, pipelined, and classical two-step converters. With minimal capacitor matching requirements and comparator offset voltage cancellation, the converter is monotonic. To minimize charge-injection errors the converter is fully differential. A high-speed comparator architecture using three comparator stages was designed to provide a gain of more than 1000, and a comparison time of less than 10 ns. The total area of the converter excluding the bonding pads is 54 kmil/sup 2/. Power dissipation is 350 mW, of which 60 mW is dissipated in the resistor string. >

Potential of MOS technologies for analog integrated circuits

Large-scale integrated circuits for many analog and combined analog-digital circuit functions are becoming feasible in N-channel and complementary metal-oxide-semiconductor technologies. Experimental results have been reported for analog to digital and digital to analog converters, a pulse-code-modulation voice encoder-decoder, and precision analog sampled-data frequency filters. Some of the key elements in these MOS circuits are precision-ratioed capacitor arrays, transistor analog switches, internally-compensated operational amplifiers, and offset-nulled comparators.