David Abercrombie

Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data

Yield enhancements in the manufacturing process today require an expensive, long and tedious physical failure analysis process to identify the root cause. In this paper we present Axiom, a new technique geared towards efficiently identifying a single dominant defect mechanism (for example in an excursion wafer) by analyzing fail data collected from the production test environment. Axiom utilizes statistical hypothesis testing in a novel way to analyze logic diagnosis data along with information on physical features in the design layout and reliably identify the dominant cause for yield loss. This new methodology was validated by applying it to a single excursion wafer produced on a 90 nm process, in which the dominant failing physical feature was correctly identified.

Value-added defect testing techniques

In the transition from micrometer to nanometer technologies, many things have changed, but customer demands for low defects-per-million (DPM) failure rates have not. Modern electronic and mechanical systems contain an ever-increasing number of semiconductor components with each component containing ever-increasing gate counts per chip. With traditional quality levels, the reliability of these systems can degrade severely. Therefore, system providers must dramatically improve the reliability of each component to maintain system reliability at all levels. This article describes advanced design-for-manufacturability (DFM) test methods that target defect coverage, yield learning, and cost. The authors argue that testing can be useful for more than filtering chips. It can directly help target test pattern provide DFM tools and reduce overall costs.

Double patterning from design enablement to verification

Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal layers. We discuss the unique design and process characteristics of LELE DP, the challenges they present, and various solutions. ○ We examine DP design methodologies, current DP conflict feedback mechanisms, and how they can help designers identify and resolve conflicts. ○ In place and route (P&R), the placement engine must now be aware of the assumptions made during IP cell design, and use placement directives provide by the library designer. We examine the new effects DP introduces in detail routing, discuss how multiple choices of LELE and the cut allowances can lead to different solutions, and describe new capabilities required by detail routers and P&R engines. ○ We discuss why LELE DP cuts and overlaps are critical to optical process correction (OPC), and how a hybrid mechanism of rule and model-based overlap generation can provide a fast and effective solution. ○ With two litho-etch steps, mask misalignment and image rounding are now verification considerations. We present enhancements to the OPCVerify engine that check for pinching and bridging in the presence of DP overlay errors and acute angles.

14nm M1 triple patterning

With 20nm production becoming a reality, research has started to focus on the technology needs for 14nm. The LELE double patterning used in 20nm production will not be able to resolve M1 for 14nm. Main competing enabling technologies for the 14nm M1 are SADP, EUV, and LELELE (referred as LE3 thereafter) triple patterning. SADP has a number of concerns of 1. density, as a layout geometry needs to stay complete as a whole, and can not be broken; 2. the complexity in SADP mask generation and debug feedback to designers; 3. the subtraction nature of the trim mask further complicates OPC and yield. While EUV does not share those concerns, it faces significant challenges on the manufacturing equipment side. Of the SADP concerns, LE3 only shares that of complexity involved in mask generation and intuitive debug feedback mechanism. It does not require a layout geometry to stay as a whole, and it benefits from the affinity to LELE which is being deployed for 20nm production. From a process point of view, this benefit from affinity to LELE is tremendous due to the data and knowledge that have been collected and will be coming from the LELE deployment. In this paper, we first recount the computational complexity of the 3-colorability problem which is an integral part of a LE3 solution. We then describe graph characteristics that can be exploited such that 3-colorability is equivalent under divide-and-conquer. Also outlined are heuristics, which are generally applied in solving computationally intractable problems, for the 3-colorability problem, and the importance in choosing appropriate worst-case exponential runtime algorithms. This paper concludes with a discussion on the new hierarchical problem that faces 3-colorability but not 2-colorability and proposals for non-3-colorability feedback mechanism.

Double patterning for 20nm and beyond: design rules aware splitting

Double patterning presents itself as one of the best candidates for pushing the limits of ArF lithography to 20nm technology node and below. It has the advantage of theoretically decreasing the minimum resolvable pitch by a factor of two, or the improvement of the process window by relaxing the lithographic conditions. Double patterning though has its own complexities. Not only sophisticated algorithms are required to simply split the design into two exposures, but these two exposures have to comply with the design manual rules. The number and the complexity of these rules tend to increase for more compact designs in terms of minimum CD and layout topology which in turns increase the coding burden on engineers to let the splitting code be aware of such numerous rules. In this context, we are proposing a new double patterning flow. It will be shown how the splitting can be done while taking into account numerous design rules. And finally, rules prioritization will be discussed in order to avoid conflicts between them.

An innovative method to automate the waiver of IP-level DRC violations

Intellectual property (IP) blocks often contain known design rule checking errors that have been “waived” by the foundry, meaning they acknowledge the error as a design rule violation, but do not consider it to be a critical yield-limiting defect. Because this waiver information is not conveyed in any consistent manner with the IP, waived IP design rule violations that reappear when the IP is integrated into a full-chip design must typically be investigated as though they are new violations. This paper will review various historic methods used to identify waived errors at the chip level, then propose a new automated method for identifying and eliminating waived errors, allowing chip designers to achieve accurate design rule checking results while minimizing debug time.

Meeting nanometer DPM requirements through DFT

As nanometer technology has increased the functionality of integrated circuits, so has it also presented challenges to acceptable yield levels. With defects per million (DPM) rates increasing, designers and manufacturers are looking for ways to enhance yield outcome. Improvements can be made by screening for defects more efficiently or by eliminating the issues leading to defects, which is the basis for any design for manufacturing (DFM) methodology. Standard test practices have become less effective for nanometer designs. However, advanced test methods show improvements can be made in three areas: increased defect coverage, increased yield learning and decreased cost.

DFM, DFT, silicon debug and diagnosis -the loop to ensure product yield

Summary form only for tutorial. After an introduction of the issues involved in the first section, the second section covers design-for-manufacturing (DFM) techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield. However, once the changes are made it is necessary to quantify their impact so that knowledge about yield contribution of different features can be fed back to design and DFM tools. Test presents an opportunity to close the loop by crafting test patterns to expose the defect prone features during automatic test pattern generation (ATPG) and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact. The third section covers design techniques (DFX) to improve testability, debuggability and diagnosability, and DFM and defect aware test generation to both meet product quality and expose yield issues at test. Section four covers the basic concepts and theoretical aspects of debug and diagnosis including algorithmic IC diagnosis, scan chain diagnosis, critical path based techniques and diagnosis of delay defects. The applications of the basic concepts and techniques for silicon debug are covered in section five. Section six covers the application of statistical diagnosis techniques to determine the features that are actually causing yield loss and their relative impact. Finally, in section seven, future trends, challenges and directions are covered.