Fedor G. Pikus

High performance lithographic hotspot detection using hierarchically refined machine learning

Under real and continuously improving manufacturing conditions, lithography hotspot detection faces several key challenges. First, real hotspots become less but harder to fix at post-layout stages; second, false alarm rate must be kept low to avoid excessive and expensive post-processing hotspot removal; third, full chip physical verification and optimization require fast turn-around time. To address these issues, we propose a high performance lithographic hotspot detection flow with ultra-fast speed and high fidelity. It consists of a novel set of hotspot signature definitions and a hierarchically refined detection flow with powerful machine learning kernels, ANN (artificial neural network) and SVM (support vector machine). We have implemented our algorithm with industry-strength engine under real manufacturing conditions in 45nm process, and showed that it significantly outperforms previous state-of-the-art algorithms in hotspot detection false alarm rate (2.4X to 2300X reduction) and simulation run-time (5X to 237X reduction), meanwhile archiving similar or slightly better hotspot detection accuracies. Such high performance lithographic hotspot detection under real manufacturing conditions is especially suitable for guiding lithography friendly physical design.

Rapid layout pattern classification

Printability of layout objects becomes increasingly dependent on neighboring shapes within a larger and larger context window. In this paper, we propose a two-level hotspot pattern classification methodology that examines both central and peripheral patterns. Accuracy and runtime enhancement techniques are proposed, making our detection methodology robust and efficient as a fast physical verification tool that can be applied during early design stages to large-scale designs. We position our method as an approximate detection solution, similar to pattern matching-based tools widely adopted by the industry. In addition, our analyses of classification results reveal that the majority of non-hotspots falsely predicted as hotspots have printed CD barely over the minimum allowable CD threshold. Our method is verified on several 45 nm and 32 nm industrial designs.

Efficient approach to early detection of lithographic hotspots using machine learning systems and pattern matching

Early lithographic hotspot detection has become increasingly important in achieving lithography-friendly designs and manufacturability closure. Fast physical verification tools employing pattern matching or machine learning techniques have emerged as great options for detecting hotspots in the early design stages. In this work, we propose a characterization methodology that provides measurable quantification of a given hotspot detection tools capability to capture a previously seen or unseen hotspot pattern. Using this methodology, we conduct a side-by-side comparison of two hotspot detection methods-one using pattern matching and the other based on machine learning. The experimental results reveal that machine learning classifiers are capable of predicting unseen samples but may mispredict some of its training samples. On the other hand, pattern matching-based tools exhibit poorer predictive capability but guarantee full and fast detection on all their training samples. Based on these observations, we propose a hybrid detection solution that utilizes both pattern matching and machine learning techniques. Experimental results show that the hybrid solution combines the strengths of both algorithms and delivers improved detection accuracy while sacrificing little runtime efficiency.

Detecting context sensitive hot spots in standard cell libraries

Advances in lithography patterning have been the primary driving force in microelectronics manufacturing processes. With the increasing gap between the wavelength of the optical source and feature sizes, the accompanying strong diffraction effects have a significant impact on the pattern fidelity of on-silicon layout shapes. Layout patterns become highly sensitive to those context shapes lying within the optical radius of influence. Under such optical proximity effects, manufacturability hot spots such as necking and bridging may occur. Studies have shown that manufacturability hot spots are pattern dependent in nature and should be considered at the design stage [1]. It is desirable to detect these hot spots as early as possible in the design flow to minimize the costs for correction. In this work, we propose a hot spot prediction method based on a support vector machine technique. Given the location of a hot spot candidate and its context patterns, the proposed method is capable of efficiently predicting whether a candidate would become a hot spot. It takes just seconds to classify thousands of samples. Due to its computational efficiency, it is possible to use this method in physical design tools to rapidly assess the quality of printed patterns. We demonstrate one such application in which we evaluate the layout quality in the boundary region of standard cells. In the conventional standard cell layout optimization process, lithography simulation is the main layout verification method. Since it is a very time-consuming process, the iterative optimization approach between simulation and layout correction [2] takes a long time and only a limited number of context patterns can be explored. We show that with the proposed hot spot prediction method, for each standard cell, a much greater context pattern space can be explored, and the context sensitivity of a hot spot candidate located near a cell boundary can be estimated.

Fast and simple modeling of non-rectangular transistors

As CMOS feature size scales down to 65nm and below, challenges for device and circuit manufacturability are emerging. As commonly seen in real designs, devices with distorted gate shapes and rough line-edges are manufactured despite the applications of aggressive resolution enhancement techniques (RET). It has been shown that such irregular gates could introduce significant extra leakage current. Existing tools and device models cannot handle non-rectangular geometries. Therefore, it is critical that a modeling flow capable of handling such irregular devices is developed and smoothly integrated into the post-lithography delay and leakage circuit analysis process. Previously proposed methods either model an irregular transistor as two different rectangular devices, one for on and the other for off state analyses; or they are difficult to be implemented. In this paper, we propose a new modeling approach that serves as a fast and simple solution to this problem and overcomes these drawbacks. We found that by adjusting both gate length and width of the equivalent device, a single equivalent rectangular device can be determined. Through TCAD and SPICE simulation experiments, we demonstrate that our model can accurately capture both on and off currents of the modeled nonrectangular gate device. The average error of our modeling approach is 1.6% for Ion and 7.5% for Ioff.

Unified process aware system for circuit layout verification

One of the challenges in establishing quantitative manufacturability metrics has been establishing a single design quality metric able to describe how a given region in the layout would perform under a specific manufacturing process. Historically, critical area analysis has been sufficient to evaluate the possible yield of a design, but as the relative importance of systematic mechanisms increases, this purely statistical approach needs to be enhanced by incorporating additional process information. In this paper we describe a consolidated metric and the system that can analyze multiple process conditions and different configurations to arrive to an optimal solution. This solution is based on a cost function which depends on the characteristics of the manufacturing process. A general form of the cost function and the parameters defining individual process impacts are discussed and, to demonstrate the system, different layout configurations are analyzed taking into account lithography process variations, random defect distributions, and recommended design rules. Since all layout configurations represent the same electrical devices, it is possible to dynamically determine the most robust layout implementation according to the cost function that incorporates the current relative importance of each yield loss contributor.

A framework for logic-aware layout analysis

In this paper, we explain a new EDA tool framework that extends the reach of Electrical DFM analysis across cross-domain applications by providing the ability to do layout analysis and logical analysis of the schematics in context. To demonstrate the effectiveness and the flexibility of the integrated environment this new framework provides, we show several real-time applications of layout verification based on the logic analysis of the circuit, where the logic analysis is performed by applying the correct design rules.

Advanced multi-patterning and hybrid lithography techniques

In this paper we present an overview of several techniques that are used when the layout pitch and feature size become significantly smaller than the minimum resolution of the lithographic process. We consider several multi-patterning (MP) techniques, in which a single layer is decomposed into two or more masks and printed in multiple stages. We also introduce the direct self-assembly (DSA) technology, where features several times smaller than the minimum lithographic resolution form spontaneously due to self-assembling, or self-organizing, formation of block copolymers.

Non-uniform yield optimization for integrated circuit layout

We demonstrate a consolidated metric that can quantitatively express design quality with respect to multiple yield loss mechanisms. Using this metric and the design analysis and optimization framework we have developed, we study the effectiveness of different layout enhancements and the effect of combining multiple enhancements in a single layout. Previous works attempted to select a single combination of design enhancements that presents the optimal trade-off between different yield loss mechanisms and optimizes the total yield. We show that the optimal solution depends on the layout features on a small scale, thus the best yield can be achieved by selecting different combinations of enhancements in different locations. We introduce a general form of the cost function and compare different layout configurations, taking into account lithography process variations, random defect distributions, and recommended design rules. Since all layout configurations represent the same electrical devices, it is possible to dynamically determine the most robust layout implementation according to the cost function that incorporates the relative importance of each yield loss contributor. We compare the globally optimized layout, where the sequence of yield enhancements is selected based on the overall design yield, with locally optimized layouts, where the enhancements are fine-tuned for each location. We show that when comparing different layout enhancements it is important to consider two types of yield tradeoffs, local tradeoffs where the same layout feature impacts several yield loss mechanisms, and global tradeoffs where the net effect of a particular type of layout enhancement depends on its location. By selectively applying yield enhancements to the areas of the layout where they are needed we can considerably improve the overall design quality.

Integrated DFM framework for dynamic yield optimization

We present a new methodology for a balanced yield-optimization and a new DFM framework which implements it. Our approach allows designers to dynamically balance multiple factors contributing to yield loss and select optimal combination of DFM enhancements based on the current information about the IC layout, the manufacturing process, and known causes of failures. We bring together the information gained from layout analysis, layout-aware circuit analysis, resolution enhancement and optical proximity correction tools, parasitics extraction, timing estimates, and other tools, to suggest the DFM solution which is optimized within the existing constraints on design time and available data. The framework allows us to integrate all available sources of yield information, characterize and compare proposed DFM solutions, quickly adjust them when new data or new analysis tools become available, fine-tune DFM optimization for a particular design and process and provide the IC designer with a customized solution which characterizes the manufacturability of the design, identifies and classifies areas with the most opportunities for improvement, and suggests DFM improvements. The proposed methodology replaces the ad-hoc approach to DFM which targets one yield loss cause at the expense of other factors with a comprehensive analysis of competing DFM techniques and trade-offs between them.