Pat LaCour

Considerations for the use of defocus models for OPC

It has been published that there is potential benefit to utilizing an OPC model based upon defocus instead of best focus processing, to give more robust patterning. While this is true with respect to gross opens and bridging problems, the available CD budget and the anticipated manufacturing consumption of defocus budgets must be considered. The net result will almost certainly always be that for gate layer processing, defocus model based OPC is not desirable. For other layers there may be favorable yield implications to running in such a manner, but the average CD in manufacturing will deviate from the design target. This paper will explore the interplay between variable focus distributions in manufacturing and the required CD control, pointing to those conditions under which a defocus model is advisable, and where it is not. Furthermore, the optimum magnitude of defocus is a compromise and has implications for final electrical performance.

Advanced layout fragmentation and simulation schemes for model-based OPCC

Traditional model based OPC software operates under a set of simple guiding principles. First, a design is fragmented into finitely sized segments, the sizes and numbers of which are limited by run-time and mask constraints. Within each fragment the intensity profile (aerial image) and edge-placement error (EPE) are calculated at a single location. Finally, the length of the entire fragment is moved to correct for the EPE at that location. This scheme has potential limitations in certain cases. For instance, cases where the aerial image contour (and therefore EPE) vary at a higher frequency than the minimum allowed fragmentation frequency. This so-called aerial image ripple problem can challenge the abilities of simple model based OPC. In addition, certain advanced RET schemes require that EPE be controlled in areas that have no adjacent mask polygon. Similarly, certain double-exposure RETs require the mutual optimization of features on multiple mask layers. Our paper will describe a flexible model based OPC scheme called Matrix OPC, which has proven capabilities of resolving these and many other advanced RET problems.

Double patterning from design enablement to verification

Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal layers. We discuss the unique design and process characteristics of LELE DP, the challenges they present, and various solutions. ○ We examine DP design methodologies, current DP conflict feedback mechanisms, and how they can help designers identify and resolve conflicts. ○ In place and route (P&R), the placement engine must now be aware of the assumptions made during IP cell design, and use placement directives provide by the library designer. We examine the new effects DP introduces in detail routing, discuss how multiple choices of LELE and the cut allowances can lead to different solutions, and describe new capabilities required by detail routers and P&R engines. ○ We discuss why LELE DP cuts and overlaps are critical to optical process correction (OPC), and how a hybrid mechanism of rule and model-based overlap generation can provide a fast and effective solution. ○ With two litho-etch steps, mask misalignment and image rounding are now verification considerations. We present enhancements to the OPCVerify engine that check for pinching and bridging in the presence of DP overlay errors and acute angles.

Effective model-based SRAF placement for full chip 2D layouts

Traditional SRAF placement has been governed by a generation of rules that are experimentally derived based on measurements on test patterns for various exposure conditions. But with the shrinking technology nodes, there are increased challenges in coming up with these rules. Model-based SRAF placement can help in improved overall process window, with less effort. This is true especially for two-dimensional layouts, where SRAF placement conflicts can provide a formidable challenge with varying patterns and sources. This paper investigates the trade-offs and benefits of using model-based SRAF placement over rule-based for various design configurations on a full chip. The impact on cost, time, process-window and performance will be studied. This paper will also explore the benefits and limitations of more complex free-form SRAF and OPC shapes generated by Inverse Lithography Technology (ILT), and strategies for integration into a manufacturable mask.

14nm M1 triple patterning

With 20nm production becoming a reality, research has started to focus on the technology needs for 14nm. The LELE double patterning used in 20nm production will not be able to resolve M1 for 14nm. Main competing enabling technologies for the 14nm M1 are SADP, EUV, and LELELE (referred as LE3 thereafter) triple patterning. SADP has a number of concerns of 1. density, as a layout geometry needs to stay complete as a whole, and can not be broken; 2. the complexity in SADP mask generation and debug feedback to designers; 3. the subtraction nature of the trim mask further complicates OPC and yield. While EUV does not share those concerns, it faces significant challenges on the manufacturing equipment side. Of the SADP concerns, LE3 only shares that of complexity involved in mask generation and intuitive debug feedback mechanism. It does not require a layout geometry to stay as a whole, and it benefits from the affinity to LELE which is being deployed for 20nm production. From a process point of view, this benefit from affinity to LELE is tremendous due to the data and knowledge that have been collected and will be coming from the LELE deployment. In this paper, we first recount the computational complexity of the 3-colorability problem which is an integral part of a LE3 solution. We then describe graph characteristics that can be exploited such that 3-colorability is equivalent under divide-and-conquer. Also outlined are heuristics, which are generally applied in solving computationally intractable problems, for the 3-colorability problem, and the importance in choosing appropriate worst-case exponential runtime algorithms. This paper concludes with a discussion on the new hierarchical problem that faces 3-colorability but not 2-colorability and proposals for non-3-colorability feedback mechanism.

OASIS-based data preparation flows: progress report on containing data size explosion

The ever-increasing complexity of integrated circuits and their enabling process technology has accelerated the increase in data volume of post-RET data which is input to the photomask manufacturing industry. OASIS - the new stream format that has been developed by a working group under the sponsorship of the SEMI Data Path Task Force enables the representation of IC layout data in a much more compact form than GDSII and facilitates the incorporation of hierarchical data into the mask-making infrastructure. OASIS achieves on average a >10x reduction in file size compared to GDSII files and structures the data in a way, which allows a straightforward translation from a hierarchical format to the required flat mask perspective. Owing to the efficiency in representing the data, OASIS files are smaller than commonly used flat exchange formats - like MEBES, thus enabling an efficient hierarchical data flow both from the processing as well as the file handling prospective. The implementation of OASIS into post-tapeout data flows will be discussed and experimental results on OASIS-based data preparation flows will be shown.

GDS-based Mask Data Preparation Flow: Data Volume Containment by Hierarchical Data Processing

As the industry enters the development of the 65nm node the pressure on the data path and tapeout flow is growing. Design complexity and increased deployment of resolution enhancement techniques (RET) result in rapidly growing file sizes, which turns what used to be the relatively simple task of mask data preparation into a real bottleneck. This discussion introduces the data preparation scheme in the mask house and analyzes its evolution. Mask data preparation (MDP) has evolved from a flow that only needed to support a single mask lithography tool data format (MEBES) with minimal data alteration steps to one which requires the support of many mask lithography tool data formats and at the same time requires significant data alteration to support the increased precision necessary for today’s advanced masks.. However, the MDP flow developed around the MEBES format and it’s derivatives still exists. The design community has migrated towards the use of hierarchical data formats and processes to control file size and processing time. MDP, which from a file size and process complexity point of view is beginning to look more and more like the advanced RET operations performed on the data prior to mask manufacturing, is still standardized on a flat data format that is poorly optimized for a growing number of mask lithography tools. Based on examples it will be shown how this complicates the data handling further. An alternate data preparation flow accommodating the larger files and re-gaining flexibility for turnaround time (TAT) and throughput management is suggested. This flow utilizes the hierarchical GDS-II format as the exchange format for mask data preparation. It complements the existing flow for the most complex designs. The introduction of a hierarchical exchange format enables the transfer of a number of necessary data preparation steps into the hierarchical domain. Data processing strategies are discussed. The paper illustrates the benefit of hierarchical processing based on GDS-II files with experimental data on file size reduction and TAT improvement for direct format conversions vs. re-fracturing as well as other processing steps. The implications for the established data preparation approaches and potential alternatives for the communication between the mask manufacturer and the customer will be discussed. The potential for further enhancements by converting to a hierarchical format that has a more efficient data representation than the commonly used GDS-II format will be discussed and illustrated.

Model-based OPC for sub-resolution assist feature enhanced layouts

Sub-resolution assist features (SRAF) have been demonstrated to provide significant process window improvement when used in combination with off-axis illumination (OAI) and attenuated phase shifted mask enhanced lithography. While some through pitch linewidth variations can be reduced through the use of SRAF, the main goal is to improve common process window, leaving the task of linewidth control to conventional optical proximity correction (OPC). OPC in combination with SRAF is also required to address 2D patterning infidelities such as corner rounding and line end shortening, for which SRAF do not provide adequate correction. Finally, OPC will be used as a means of recovering process window that may be lost in layout situations that result in poor SRAF coverage. With an industry wide migration form rules-based OPC to iterative, model-based solutions, the integration of inherently rules based SRAF generation and model-based OPC has to be investigated.

Impact of process variation on 65nm across-chip linewidth variation

The latest improvements in process-aware lithography modeling have resulted in improved simulation accuracy through the dose and focus process window. This coupled with the advancements in high speed, full chip grid-based simulation provide a powerful combination for accurate process window simulation. At the 65nm node, gate CD control becomes ever more critical so understanding the amount of CD variation through the full process window is crucial. This paper will use the aforementioned simulation capability to assess the impact of process variation on ACLV (Across-Chip Linewidth Variation) and critical failures at the 65nm node. The impact of focus, exposure, and misalignment errors in manufacturing is explored to quantify both CD control and catastrophic printing failure. It is shown that there is good correlation between predicted and experimental results.

Implementation of adaptive site optimization in model-based OPC for minimizing ripples

The OPC treatment of aerial mage ripples (local variations in aerial contour relative to constant target edges) is one of the growing issues with very low-k1 lithography employing hard off-axis illumination. The maxima and minima points in the aerial image, if not optimally treated within the existing model based OPC methodologies, could induce severe necking or bridging in the printed layout. The current fragmentation schemes and the subsequent site simulations are rule-based, and hence not optimized according to the aerial image profile at key points. The authors are primarily exploring more automated software methods to detect the location of the ripple peaks as well as implementing a simplified implementation strategy that is less costly. We define this to be an adaptive site placement methodology based on aerial image ripples. Recently, the phenomenon of aerial image ripples was considered within the analysis of the lithography process for cutting-edge technologies such as chromeless phase shifting masks and strong off-axis illumination approaches [3,4]. Effort is spent during the process development of conventional model-based OPC with the mere goal of locating these troublesome points. This process leads to longer development cycles and so far only partial success was reported in suppressing them (the causality of ripple occurrence has not yet fully been explored). We present here our success in the implementation of a more flexible model-based OPC solution that will dynamically locate these ripples based on the local aerial image profile nearby the features edges. This model-based dynamic tracking of ripples will cut down some time in the OPC code development phase and avoid specifying some rule-based recipes. Our implementation will include classification of the ripples bumps within one edge and the allocation of different weights in the OPC solution. This results in a new strategy of adapting site locations and OPC shifts of edge fragments to avoid any aggressive correction that may lead to increasing the ripples or propagating them to a new location. More advanced adaptation will be the ripples-aware fragmentation as a second control knob, beside the automated site placement.