David Andrew Inglis

A 200 mW 3.3 V CMOS color camera IC producing 352/spl times/288 24 b video at 30 frames/s

Recent advances in CMOS imaging technology enable the creation of single-chip digital cameras that offer system designers fully-digital interfaces, reduced part counts, and low-power dissipation. A PC-based camera system is described using a single-chip camera. The chip produces digital video data that is fed to the host over a standard interface. The host adjusts operation of the camera by setting frame rate, exposure time, analog gains, and color processing coefficients. Frame-rate functions, such as exposure control and white balance algorithms, are in software on the host, while pixel-rate tasks requiring intensive computation, such as color interpolation, color correction, and calculation of image statistics are in hardware on the camera chip.

A gigabit transceiver chip set for UTP CAT-6 cables in digital CMOS technology

1000BASE-T is a standard defining a 1 Gb/s Ethernet physical layer based on PAM-5 signalling, using bi-directional (full-duplex) transmission on four pairs of UTP Category 5, in order to re-use the already existing horizontal cabling infrastructure. Because of the use of full-duplex transmission over four pairs (due to CAT-5 100 MHz bandwidth limitations), this approach requires echo and near-end cross-talk (NEXT) cancellation. The monolithic integration of this system is challenging. An alternative approach is to use Category-6 cables which offer a bandwidth specified up to 250 MHz. This work is based on full-duplex 1 Gb/s transmission on 4 pairs of CAT-6 cabling, where each pair is used in uni-directional fashion (2 pairs 500 Mb/s transmit, 2 pairs 500 Mb/s receive, avoiding the need for echo cancellation. The measured frequency response of a CAT-6 cable compared to CAT-5 is shown (both are scaled to worst-case envelopes). The line code chosen here is the same as in the 1000BASE-T standard, 5-level PAM modulation, but at twice the baud-rate (250 M baud instead of 125 M baud) thus achieving 500 Mb/s on each pair instead of 250 Mb/s as in CAT-5. The paper shows the overall system block diagram. For simplicity the test-chip contains only one transmitter/receiver (2 pairs)-a complete gigabit transceiver is obtained by using two test chips.