Patrik Larsson

Resonance and damping in CMOS circuits with on-chip decoupling capacitance

Design of on-chip decoupling capacitance and modeling of resonance effects in the power supply network of CMOS integrated circuits is addressed. The modeling is based on mathematical limits proving that damping will be low, resulting in resonance unless careful design is used. Design strategies that reduce resonance are discussed. It is shown that an optimal parasitic resistor in series with the decoupling capacitor gives a maximum damping factor of 0.5 and practical values are within the range 0.3-0.4. Examples of digital circuits show that proper design of on-chip decoupling capacitance may reduce the number of bonding wires by an order of magnitude. The modeling and design suggestions are also applicable to mixed-mode circuits. In particular, sampled analog networks benefit with a potentially higher sampling rate if enhanced damping is introduced during design.

di/dt Noise in CMOS Integrated Circuits

This is an overview paper presenting di/dtnoise from a designer‘s perspective. Analysis and circuit designtechniques are presented taking package parasitics into account.The main focus is on digital CMOS design, but analysis and designsuggestions can easily be extended to mixed-mode design.

Reconfigurable hardware for efficient implementation of programmable FIR filters

We present the architecture of a programmable FIR filter for use in DSP and communication applications. A filter with this architecture is capable of running a wide variety of single-rate and multirate filtering algorithms with low latency. Flexibility is achieved by distributed register files that store input data and filter coefficients. The functionality of the filter is programmed by a set of pipelined control signals that are independent of the filter length. We demonstrate how to generate these control signals for a variety of configurations. In addition to its flexibility, the architecture is scalable, modular, and has no broadcast signals, making it ideally suited for VLSI implementations.

Transition reduction in carry-save adder trees

By taking advantage of the redundancy in a 4-2 compressor, we reduce the number of transitions in carry-save adder trees that are common in large multipliers. Three new 4-2 compressors are proposed. These are used in different configurations to reduce the probability of a transition in the global carry wires by up to 40% over current techniques. Power reductions are demonstrated with the use of a 4-tap FIR filter module and a 54/spl times/54-bit multiplier. Transistor level circuit simulations indicate 5-6% power reduction with no increase in delay.

Adaptive phase shifting in FIR filters with application to equalizers

A method for phase-adaptation in FIR filters is introduced and applied to fractionally-spaced equalizers. The technique removes the need of a high-precision rotator-derotator pair when training a blind equalizer with the constant modulus algorithm (CMA). The phase-correcting CMA (PCMA) provides an equalizer with the same convergence reliability as the CMA and the hardware cost comparable to the reduced constellation algorithm (RCA). The technique can also be used to avoid the most common cases of ill-convergence in the RCA.