Erin C. Jones

Electrical characterization of germanium p-channel MOSFETs

In this letter, we report germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer. The fabricated devices show 2 /spl times/ higher transconductance and /spl sim/ 40% hole mobility enhancement over the Si control with a thermal SiO/sub 2/ gate dielectric, as well as the excellent subthreshold characteristics. For the first time, we demonstrate Ge MOSFETs with less than 100-mV/dec subthreshold slope.

Extreme scaling with ultra-thin Si channel MOSFETs

We examine the scaling limits for planar single gate technology using the ultra-thin Si channel MOSFET. Characteristics for extreme scaled devices with physical gate lengths down to 6 nm and SOI channels as thin as 4 nm are presented. For the first time, we report ring oscillators with 26 nm gate lengths and ultra-thin Si channels.

High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric

We report Ge p-channel MOSFETs with a thin gate stack of Ge oxynitride and LTO on bulk Ge substrate without a Si cap layer. Excellent device characteristics (IV and CV) are achieved with subthreshold slope 82mV/dec. /spl sim/40% hole mobility enhancement is obtained over the Si control with a thermal SiO/sub 2/ gate dielectric. To our knowledge, this is the first demonstration of Ge MOSFETs with less than 10nm thick gate dielectric and less than 100mV/dec subthreshold slope.

Two gates are better than one [double-gate MOSFET process]

A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of the back-gate layer after the S/D structure is in place. This allows coupling the silicon thickness control inherent in a planar, unpatterned layer with VLSI self-alignment techniques and also gives independently controlled front and back gates. The demanding structure led to process innovations primarily in front-end CMP, where planarity within 5 nm was achieved on an 8-in diameter wafer as well as in silicided silicon source/drain sidewalls, with minimal encroachment of the silicide. Double-gate FET (DGFET) operation is demonstrated, with good transport at both interfaces. Dense circuit layouts are achieved with multifinger devices, and logic inverters with back-gate-controlled load current as well as NOR logic using the two gates of a single transistor as inputs are demonstrated.

Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs

Demonstrated double-gate devices with excellent drive current and short-channel-effect control. The double-gate devices exhibit ideal linear, sub-threshold slope of 60 mV/dec and better than ideal saturated sub-threshold slope of 55 mV/dec. The effective mobility in all device structures follows the universal mobility curve. The symmetric double-gate offers 20% mobility enhancement over a GP device at 1.0 V gate over-drive. Because the double-gate can be operated at a much lower effective-field, substantial mobility enhancement (>2X) over scaled bulk CMOS can be achieved. For the first time, DC operation of double-gate CMOS inverters are demonstrated down to Vdd=0.3 V.

Characterization of the silicon on insulator film in bonded wafers by high resolution x-ray diffraction

High resolution x-ray diffraction (HRXRD) is proposed as a nondestructive tool for the characterization of the silicon on insulator (SOI) film in bonded wafers. Although the bonded stack may consist of many amorphous layers, the measured diffraction spectra only show the crystalline SOI layer, thus providing a direct measurement of the film. We have demonstrated that HRXRD is capable of accurately measuring the film thickness, the tilt of the film planes with respect to the substrate planes, and the rotation misalignment of the bonded film with respect to the carrier substrate. SOI films with thicknesses down to 30 nm were readily measured with accuracy better than 1%. It is shown that an angular separation between the layer and the substrate diffraction peaks is maintained due to an unintentional miscut which usually exists in the starting wafers used for bonding. This angular separation is unique to bonded wafers as opposed to separation by implanted oxygen (SIMOX) wafers where the layer and substrate p...

High-resolution x-ray diffraction for characterization and monitoring of silicon-on-insulator fabrication processes

High-resolution x-ray diffraction (HRXRD) was used to monitor silicon-on-insulator (SOI) device fabrication processes. The use of HRXRD is attractive since it is nondestructive and can be applied directly to product wafers. We show the usefulness of this technique for the characterization of amorphizing implants for shallow junctions, solid phase recrystallization of implanted junctions, cobalt-silicide formation, and oxidation; all are critical processes for complementary metal oxide semiconductor device fabrication on SOI. We also found the technique applicable to multilayered SOI structures fabricated by wafer bonding, where the tilt and rotation of each SOI layer with respect to the handle substrate, allowed us to obtain independent measurements of each SOI film.

High performance double-gate device technology challenges and opportunities

The double-gate FET is widely recognized as the prime candidate for the ultimate scaling of FETs to the shortest channel length. From the device integration point of view, the attainment of low extrinsic resistance, carrier transport in the double-gated thin silicon channel and threshold voltage control, remained significant obstacles to high-performance double-gate CMOS structures. We report how these issues were addressed to achieve world-record double-gate device performance. The second gate in a double-gate device can be utilized for low-power and mixed-signal applications. The flexibility of individually controlling the two gates provides opportunities for overall system performance improvement. Ultra-low voltage operation of double-gate CMOS inverters was demonstrated. Finally, we discuss the migration of existing circuit/layout designs to double-gate device technology.

Examination of hole mobility in ultra-thin body SOI MOSFETs

This paper presents an experimental examination of hole mobility in ultra-thin body (UTB) SOI MOSFETs, covering wide ranges of T/sub SOI/ (between /spl sim/3.7 nm and /spl sim/50 nm), and temperature (between /spl sim/79 K and /spl sim/320 K). This paper addresses the observed strong degradation of hole mobility at extremely thin T/sub SOI/, proposing an additional surface roughness scattering mechanism for the thinnest samples due to the perturbation of the conducting band potential stemming from spatial confinement.

An experimental study on transport issues and electrostatics of ultrathin body SOI pMOSFETs

We present an experimental study of the transport properties (low field hole mobility /spl mu//sub h/) and electrostatics (threshold voltage V/sub th/, and gate-to-channel capacitance C/sub gc/) of ultrathin body (UTB) SOI pMOSFETs using a large RingFet structure. Body thicknesses were /spl sim/4.3 nm to 50 nm. We find that 1) hole mobility decreases significantly as T/sub Si/<10 nm, and tends to show negligible dependence on the transverse electric field for extremely thin T/sub Si/ (<6 nm) and 2) a V/sub th/ shift of /spl sim/150 mV occurs over the studied T/sub Si/ range, accompanied by enhancement of weak inversion capacitance in thin body devices. Simulations were performed to provide insight into the experimental observations.