David B. Spratt

Shallow junction formation by dopant diffusion from in situ doped polycrystalline silicon chemically vapor deposited in a rapid thermal processor

Shallow n+‐p junctions were formed by utilizing an in situ doped thin polycrystalline silicon layer as a diffusion source. The in situ arsenic‐doped polycrystalline silicon films were deposited by rapid thermal processing chemical vapor deposition. The dopant pileup phenomena were observed at both the polycrystalline silicon/silicon interface and at the surface. The dopant concentrations were higher when the deposition temperatures were lower. The observed pileup phenomena at the polycrystalline silicon/silicon interface were temperature dependent and mainly due to the segregation of arsenic at the grain boundary. The dopant distribution was mainly due to the grain boundary diffusion and grain growth mechanisms. Extremely shallow n+‐p junctions were achieved and laterally uniform delineated junctions were observed. The dopant concentration in the Si substrate drops two orders of magnitude in less than 500 A.

Selective epitaxial growth with oxide‐polycrystalline silicon‐oxide masks by rapid thermal processing chemical vapor deposition

We have used rapid thermal processing chemical vapor deposition for Si selective epitaxial growth using a mask consisting of a sandwich structure of SiO2 on doped polycrystalline Si on SiO2. Lateral polycrystalline Si growth from the sidewalls of the polycrystalline Si layer was also observed and resulted in polycrystalline ‘‘bumps’’ along the mask sidewalls. Otherwise, the epitaxial Si layer was defect‐free.

Total dose radiation characteristics of SOI MOSFETs fabricated using ISLANDS technology

Total-dose-radiation results for n- and p-channel silicon-on-insulator (SOI) MOSFETs fabricated using ISLANDS (oxidation of porous silicon) technology and subjected to Co-60 gamma radiation are reported. The back-gates of both n- and p-channel transistors were hard to 1 Mrad(Si) with either -5 or 0 V on the substrate during irradiation. The buildup of radiation-induced interface traps at the back-gate of n-channel MOSFETs compensated for the threshold voltage shift due to oxide-trapped charges. The front-gate hardness was similar to that of bulk MOSFETs. >

Growth of in situ doped silicon epitaxial layer by rapid thermal processing

In this letter, rapid thermal processing chemical vapor deposition has been used to grow high quality in situ doped silicon epitaxial layers. Device quality epilayers have been obtained for both boron and phosphorus doping with abrupt dopant transition profiles. The mobility values of these doped epilayers are very close to the values for bulk silicon under the same doping concentration.