Robert H. Eklund

Secondary ion mass spectroscopy characterization of the deuterium sintering process for enhanced-lifetime complementary metal–oxide–semiconductor transistors

We have investigated the lifetime improvements in complementary metal–oxide–semiconductor transistors with nitride sidewalls by the deuterium sintering process. We report the incorporation of deuterium (D) at the gate SiO2/Si interface (overcoming the diffusion barrier of nitride sidewalls) and mean lifetime improvements by a factor of 15. Sintering temperatures ranged from 400 to 480 °C, and the D concentration inside the furnace varied from 10% (in ultra-high purity nitrogen) to 100% with sintering times between 30 and 150 min. We performed secondary ion mass spectrometry to obtain the depth profiles of hydrogen (H) and D in the sintered transistors. The measured D/H concentration ratio at the SiO2/Si interface correlates directly with the sintering parameters and the measured transistor lifetime improvements.

BiCMOS Process Technology

For high performance LSI and VLSI digital circuit applications, BiCMOS technology has become predominantly driven from a CMOS processing base. The principle reason for this is that LSI and VLSI digital BiCMOS circuits tend to be CMOS-intensive because of power dissipation limitations (for example, high density ECL I/O SRAMs and gate arrays). The CMOS-intensive nature of these circuits requires a process technology that will result in the highest possible CMOS performance. Consequently, BiCMOS fabrication technology tends to be CMOSbased, and the process steps needed to realize a high performance bipolar device are usually merged with a core CMOS process flow [3.1,3.2,3.3]. In the case of analog BiCMOS, the increasing demand to have on-board digital logic integration has also resulted in these processes being CMOS-oriented.

Remote plasma nitridation, deuterium anneal and pocket implant effects on NMOS hot carrier reliability

Abstract There are several advanced processes which are being actively studied as candidates for sub-0.25 μm technology. This paper studies the effects on NMOS hot carrier reliability from remote plasma nitrided oxide (RPNO), deuterium anneal and pocket implant. It is found that RPNO will not affect the SiO 2 /Si interface. The hot carrier reliability is better for the same device channel current. This is due to making the effective oxide thickness thinner and achieving the same drive current with longer channel length. The deuterium anneal can improve the hot carrier reliability, even with nitride sidewall, if proper annealing is done. While the pocket implant can reduce short channel effects, the hot carrier lifetime is degraded unless optimization is done.