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Dive into the research topics where David Barge is active.

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Featured researches published by David Barge.


european solid-state device research conference | 2014

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs

F. Andrieu; M. Cassé; E. Baylac; P. Perreau; Olivier Nier; D. Rideau; Remy Berthelon; F. Pourchon; A. Pofelski; B. De Salvo; Claire Gallon; Vincent Mazzocchi; David Barge; C. Gaumer; Olivier Gourhant; A. Cros; Vincent Barral; R. Ranica; N. Planes; W. Schwarzenbach; E. Richard; E. Josse; O. Weber; F. Arnaud; M. Vinet; O. Faynot; M. Haond

We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on SOI (SGOI) in terms of short channel hole mobility and ION. We analyse the layout effects in sSOI/sSGOI transistors, ring oscillators (ROs) and SRAMs for different Ge amounts and strains and report for the first time the carrier mobility in sSOI/sSGOI vs. the active length (Lac). Through a layout optimization, a high uniaxial strain can be created, boosting the carrier mobility in both sSOI/sSGOI by 10/20% and ensuring the scalability of the planar FDSOI architecture for the 10nm node.


Thin Solid Films | 2012

Faceting and nanostructure effects in Si and SiGe epitaxy

Didier Dutartre; Birgit Seiss; Yves Campidelli; Denis Pellissier-Tanon; David Barge; R. Pantel


Applied Surface Science | 2016

Low thermal budget for Si and SiGe surface preparation for FD-SOI technology

M. Labrot; F. Cheynis; David Barge; P. Müller; M. Juhel


Meeting Abstracts | 2007

Gate Oxide Cleans on Single Wafer Tool

Philippe Garnier; Tony Vessa; Anne Sophie Larrea; B. Pernet; Y. Gomez; David Barge; A. Torres; B. Tavel; C. Henderson; Didier Lévy


PRiME 2016/230th ECS Meeting (October 2-7, 2016) | 2016

Improvement of Boron Doping in SiGe Raised Sources and Drains for FD-SOI Technology by Carbon Incorporation

Maxime Labrot; F. Cheynis; David Barge; Marc Juhel; P. Müller


Archive | 2012

METHOD FOR FORMING THE GATE INSULATOR OF A MOS TRANSISTOR

Olivier Gourhant; David Barge; Clement Gaumer; Mickael Gros-Jean


Physica Status Solidi (c) | 2016

Technological enhancers effect on Ni0.9Co0.1 silicide stability for 3D sequential integration

Fabien Deprat; Fabrice Nemouchi; C. Fenouillet-Beranger; Philippe Rodriguez; Sylvain Joblot; Magali Gregoire; David Barge; Patrice Gergaud; Nils Rambal; Perrine Batude; M. Vinet


Archive | 2016

METHOD FOR FABRICATING A TRANSISTOR WITH A RAISED SOURCE-DRAIN STRUCTURE

Didier Dutartre; David Barge


2014 ECS and SMEQ Joint International Meeting (October 5-9, 2014) | 2014

Ge Condensation Using Rapid Thermal Oxidation for SGOI Substrate Preparation

Olivier Gourhant; Clément Pribat; David Barge; Vincent Mazzocchi; F. Andrieu; F. Abbate; Marc Juhel; Clement Gaumer; Elise Baylac; Alexandre Pofelski; Maud Bidaud; Germain Serventon


Microelectronic Engineering | 2017

Improvement of etching and cleaning methods for integration of raised source and drain in FD-SOI technologies

M. Labrot; F. Cheynis; David Barge; Patrick Maury; M. Juhel; S. Lagrasta; P. Müller

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F. Cheynis

Aix-Marseille University

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P. Müller

Aix-Marseille University

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