Olivier Gourhant

The role of ultraviolet radiation during ultralow k films curing: Strengthening mechanisms and sacrificial porogen removal

This work proposes a fundamental understanding of structural transformation occurring during porogen extraction from as-deposited ultralow k (ULK) materials when exposed to ultraviolet (UV) radiation during thermal curing. Specific explanations are provided for as deposited films at high temperature (T>250 °C). This temperature range is sufficient to assess thin-film stability. Two distinguished regimes were identified in the curing process. During the first stage, the film shrinks strongly in similar proportion to SiCH3 break. Preferential impact of UV radiation on hydrocarbon porogen bonds leads also to a break of SiCH3 structures. In this work, 5 min of curing is enough to remove the porogen and create the max of porosity (33%). After the porogen removal step, the porous film shrinks under UV radiation leading to an increase of SiOSi bond concentration. A structural rearrangement of the bulk is initiated since the porogen is totally evacuated from the film. The increase of normalized infrared SiOSi pea...

Crosslinking of porous SiOCH films involving Si–O–C bonds: Impact of deposition and curing

This paper focuses on the properties of nanoporous SiOCH thin films deposited using a porogen approach by plasma enhanced chemical vapor deposition. The impact of deposition temperature, porogen loading and porogen removal treatment is investigated using Fourier transform infrared spectroscopy, solid-state nuclear magnetic resonance analysis, and electrical and mechanical measurements. This work shows that a higher deposition temperature allows limiting the film shrinkage during the porogen removal treatment and leads to the best compromise in term of electrical and mechanical properties. Beside, the effect of Si–O–C bonds on the enhancement of mechanical properties is promoted since a typical crosslinking mechanism is highlighted in case of ultraviolet curing.

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs

We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on SOI (SGOI) in terms of short channel hole mobility and ION. We analyse the layout effects in sSOI/sSGOI transistors, ring oscillators (ROs) and SRAMs for different Ge amounts and strains and report for the first time the carrier mobility in sSOI/sSGOI vs. the active length (Lac). Through a layout optimization, a high uniaxial strain can be created, boosting the carrier mobility in both sSOI/sSGOI by 10/20% and ensuring the scalability of the planar FDSOI architecture for the 10nm node.

Grazing incidence small angle x-ray scattering study of the structure of nanoporous ultralow-k dielectrics prepared by plasma enhanced chemical vapor deposition

This paper focuses on the structure of nanoporous SiOCH thin films deposited using a porogen approach by plasma enhanced chemical vapor deposition (PECVD). The grazing incidence small angle x-ray scattering signal demonstrates the existence of a biphase pattern in hybrid films, deposited by PECVD. After porogen removal, there are few differences between pore pattern of optimized ultraviolet (UV) illuminated and thermally treated samples: anisotropy of the pore pattern is observed in both samples, probably due to the porogen degradation. Finally, a kinetic study of porogen degradation by UV shows that the porous structure develops in only a few minutes.

A novel dual isolation scheme for stress and back-bias maximum efficiency in FDSOI Technology

A novel dual isolation scheme with both Shallow Trench Isolation (STI) and local oxidation, so called Dual Isolation by Trenches and Oxidation (DITO), is presented to maximize the stress induced by SiGe channel and the back-biasing efficiency at the same time in FDSOI technology. DITO integration experimentally demonstrates +36% pMOSFET drive current at same leakage, which is translated into −23% ring-oscillator delay reduction at a supply voltage of Vdd=0.8V. It is found that this gain is attributed to 0.45GPa saved compressive stress in the longitudinal direction, compared to the standard STI isolation. On top of that, DITO enables the Vt tuning in an extended range for both nMOS and pMOS independently through back-bias application in both reverse and forward modes. +29% and 1 decade leakage extensions are provided by this full range Vt tuning compared to the standard single STI and well FDSOI architecture where only one back-bias mode is allowed. DITO thus leverages highly-stressed and highly-tunable devices for both high performance and low power applications.

Oxidation kinetics of Si and SiGe by dry rapid thermal oxidation, in-situ steam generation oxidation and dry furnace oxidation

The fabrication of ultrathin compressively strained SiGe-On-Insulator layers by the condensation technique is likely a key milestone towards low-power and high performances FD-SOI logic devices. However, the SiGe condensation technique still requires challenges to be solved for an optimized use in an industrial environment. SiGe oxidation kinetics, upon which the condensation technique is founded, has still not reached a consensus in spite of various studies which gave insights into the matter. This paper aims to bridge the gaps between these studies by covering various oxidation processes relevant to todays technological needs with a new and quantitative analysis methodology. We thus address oxidation kinetics of SiGe with three Ge concentrations (0%, 10%, and 30%) by means of dry rapid thermal oxidation, in-situ steam generation oxidation, and dry furnace oxidation. Oxide thicknesses in the 50 A to 150 A range grown with oxidation temperatures between 850 and 1100 °C were targeted. The present work shows first that for all investigated processes, oxidation follows a parabolic regime even for thin oxides, which indicates a diffusion-limited oxidation regime. We also observe that, for all investigated processes, the SiGe oxidation rate is systematically higher than that of Si. The amplitude of the variation of oxidation kinetics of SiGe with respect to Si is found to be strongly dependent on the process type. Second, a new quantitative analysis methodology of oxidation kinetics is introduced. This methodology allows us to highlight the dependence of oxidation kinetics on the Ge concentration at the oxidation interface, which is modulated by the pile-up mechanism. Our results show that the oxidation rate increases with the Ge concentration at the oxidation interface.The fabrication of ultrathin compressively strained SiGe-On-Insulator layers by the condensation technique is likely a key milestone towards low-power and high performances FD-SOI logic devices. However, the SiGe condensation technique still requires challenges to be solved for an optimized use in an industrial environment. SiGe oxidation kinetics, upon which the condensation technique is founded, has still not reached a consensus in spite of various studies which gave insights into the matter. This paper aims to bridge the gaps between these studies by covering various oxidation processes relevant to todays technological needs with a new and quantitative analysis methodology. We thus address oxidation kinetics of SiGe with three Ge concentrations (0%, 10%, and 30%) by means of dry rapid thermal oxidation, in-situ steam generation oxidation, and dry furnace oxidation. Oxide thicknesses in the 50 A to 150 A range grown with oxidation temperatures between 850 and 1100 °C were targeted. The present work sho...

Gate stack solutions in gate-first FDSOI technology to meet high performance, low leakage, V T centering and reliability criteria

A unique gate stack solution has been found in gate-first FDSOI to meet at the same time high performance, low leakage, V_T centering and reliability criteria for NMOS and PMOS with T_inv=12.5Å and 14Å, respectively. Trade-offs between those characteristics are highlighted in this paper through process knob variations, including the interfacial layer (IL) formation, the IL surface treatment and the drive-in anneal temperature. The path allowing the construction of both low-V_T high speed logic, reaching 7.2ps/stg FO3 ring oscillator delay at V_nom=0.8V, and high-V_T low leakage SRAM, achieving 3pA/cell standby leakage at V_nom=0.8V, is demonstrated through gate workfunction engineering and gate leakage optimization. On top of this result, 5 years BTI and 10 years TDDB reliability lifetime were qualified at V_max=0.945V, 125°C.