Didier Dutartre

0.13

This paper presents a complete 0.13 μm SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280 GHz fT/fMAX) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2 fF/μm2 high-linearity MIM capacitor and complementary double gate oxide MOS transistors. Details are given on HBT integration, reliability and models as well as on back-end devices models.

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A new concept of dielectric pockets is proposed allowing suppression of short-channel effects (SCEs) and DIBL without increasing the channel doping. The dielectric pockets have been implanted into 0.15-/spl mu/m PMOS devices showing substantial efficiency in reducing SCE and I/sub OFF/ current without altering the current drive. The dielectric pockets thus embody the ideal pocket architecture.

m SiGe BiCMOS Technology Fully Dedicated to mm-Wave Applications

In nanometer MOSFETs, because of the small channel size, mesoscopic and even quantum effects can come into play. We have fabricated l6 nm NMOS devices featuring I/sub on/=400 /spl mu/A//spl mu/m and I/sub off/=0.8 /spl mu/A//spl mu/m and demonstrate that the FET principle is still confirmed at room temperature. We have deliberately used a non-overlapped SD/gate architecture, showing that, with adapted channel doping, it not only performs equally as well as the overlapped one, but also shows 1000/spl times/ reduced dispersion and is easily manufacturable. Finally, we show that quantization of energy in the channel motivates a study of performance at low temperature, and that the leading effect at low temperature and low voltage is Coulomb blockade.

Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices

This paper describes a 230-GHz self-aligned SiGeC heterojunction bipolar transistor developed for a 90-nm BiCMOS technology. The technical choices such as the selective epitaxial growth of the base and the use of an arsenic-doped monocrystalline emitter are presented and discussed with respect to BiCMOS performance objectives and integration constraints. DC and high-frequency device performances at room and cryogenic temperatures are given. HICUM model agreement with the measurements is also discussed. Finally, building blocks with state-of-the-art performances for a CMOS compatible technology are presented: A ring oscillator with a minimum stage delay of 4.4 ps and a 40-GHz low-noise amplifier with a noise figure of 3.9 dB and an associated gain of 9.2 dB were fabricated.

16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation

For the first time, both GAA and bulk devices were shown to be operational on the same chip. Not all issues have been solved yet (gate materials, access resistance) but already the first-try results are very encouraging: I/sub on/=170 /spl mu/A//spl mu/m@1.2 V and gate oxide of 20 /spl Aring/. Thanks to the GAA intrinsic immunity to SCE, its DIBL was as small as 10 mV compared with 600 mV on bulk control devices. Calibrating a 2D simulator on this electrical data, the performance of the GAA was estimated to be at least 1500 /spl mu/A//spl mu/m@ 1 V with comfortable gate oxide of 20 /spl Aring/, once having corrected for the large R/sub access/ (/spl sim/3000 /spl Omega/), that was simply due to non-optimal mask layout used in this first device realization.

230-GHz self-aligned SiGeC HBT for optical and millimeter-wave applications

In this paper, the first 80 nm SON MOSFETs are presented, demonstrating the electrical viability of the SON architecture. The transistors have a 20 nm thick Si-film channel, isolated from the bulk by a 20 nm dielectric layer. The electrical results show significant improvement (/spl sim/30%) compared with bulk reference devices. In particular, drive current and transconductance are improved due to the better effective field-inversion charge compromise, and SCE due to the thinness of the junctions and of the channel. These electrical results are then used to calibrate the ISE simulator and to make predictions on SON performances with more aggressive gate length and Tox. These predictions show the potential of the SON architecture for future CMOS generations.

50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process

A 200 mm 0.35 /spl mu/m silicon-germanium heterojunction bipolar transistor (SiGe HBT) technology involving epitaxially-aligned polysilicon emitters is described. The devices are shown to combine the high speed performances typical for poly-Si emitter SiGe base devices (f/sub max/ up to 70 GHz) and the low 1/f noise properties of monocrystalline emitter structures (noise figure-of-merit KB as low as 7.2/spl times/10/sup -10/ /spl mu/m/sup 2/). Statistical current gain data are used to demonstrate the manufacturability of this innovative SiGe HBT technology.

First 80 nm SON (Silicon-On-Nothing) MOSFETs with perfect morphology and high electrical performance

Utilizing the SON (silicon on nothing) process, highly performant double gate devices have been processed in a planar configuration. Two families of devices were obtained (high performance and low power) with very high Ion/Ioff trade off. Drive currents of 1954 /spl mu/A//spl mu/m (Ioff = 283 nA//spl mu/m) and 1333 /spl mu/A//spl mu/m (Ioff = 1 nA//spl mu/m) are obtained at 1.2 V with Tox = 20 /spl Aring/ and Lgate = 70 nm. DIBL is very well controlled, measured below 60 mV for gates as short as 40 nm. These features place our devices among the most performant ever reported.

A high-speed low 1/f noise SiGe HBT technology using epitaxially-aligned polysilicon emitters

This paper presents a complete 0.13 mum SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280GHz fT/fMAX) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2fF/mum2 high-linearity MIM capacitor and complementary double gate oxide MOS transistors.

Highly performant double gate MOSFET realized with SON process

A robust 0.25 /spl mu/m double-poly SiGe HBT structure using non selective epitaxy has been developed. The device features 70/90 GHz f/sub T//f/sub max/ with pure SiGe base in 0.25 /spl mu/m BiCMOS technology. Performances up to 120/100 GHz f/sub T//f/sub max/ are demonstrated for SiGe:C base transistors.