David D. Wilmoth

Erasable programmable memory including buried diffusion source/drain lines and erase lines

Method of making a high-speed 2-transistor cell for programmable/EEPROM devices with separate read and write transistors

Reference circuit for integrated memory arrays having virtual ground connections

Apparatus and method for programming field programmable arrays

Equalized biased array for proms and eproms

Wired logic functions on FPGA's

Array discharge for biased array

Extra row for testing programmability and speed of ROMS

Field programmable gate array device with antifuse overcurrent protection

High speed CMOS transition detector circuit